From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C086C48BCF for ; Sun, 13 Jun 2021 08:49:13 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1EC05610C7 for ; Sun, 13 Jun 2021 08:49:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1EC05610C7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 769C380EC7; Sun, 13 Jun 2021 10:49:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id F04C980EC8; Sun, 13 Jun 2021 10:49:06 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6021680A22 for ; Sun, 13 Jun 2021 10:49:01 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=elly.siew.chin.lim@intel.com IronPort-SDR: C+6pDVxHEORJnEWCaHzDw4n9Lwb7QQJXdCgztaRiSvSXO5IBlL9N54OGfgEd62c1buHDNGcCjO 2jzA+/YfU0lA== X-IronPort-AV: E=McAfee;i="6200,9189,10013"; a="185398410" X-IronPort-AV: E=Sophos;i="5.83,270,1616482800"; d="scan'208";a="185398410" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2021 01:48:58 -0700 IronPort-SDR: Hf9uVqLss/tjtc8LtSAcfFEy2+fHEC3/7VWEbEjoaQrKl8AN6UhDMYRpm47eoYDm66UrJGgDLu taHvaf2RQ1yA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,270,1616482800"; d="scan'208";a="441941606" Received: from pg-iccf0307.altera.com ([10.104.1.103]) by orsmga007.jf.intel.com with ESMTP; 13 Jun 2021 01:48:55 -0700 From: Siew Chin Lim To: u-boot@lists.denx.de Cc: Marek Vasut , Ley Foon Tan , Simon Goldschmidt , Tien Fong Chee , Dalon Westergreen , Simon Glass , Yau Wai Gan , Siew Chin Lim Subject: [v3 00/17] Add Intel N5X SoC support Date: Sun, 13 Jun 2021 16:48:35 +0800 Message-Id: <20210613084852.30868-1-elly.siew.chin.lim@intel.com> X-Mailer: git-send-email 2.13.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This is the 3rd version of patchset to add Intel N5X SoC[1] support. Intel N5X SoC is with a 64-bit quad core ARM Cortex-A53 MPCore hard processor system (HPS). New IPs in N5X are clock manager and DDR subsystem, other IPs have minor changes compared to Agilex. Intel N5X SoC supports legacy boot without ATF for debugging purpose, ATF boot, and ATF boot with VAB enabled. [1]: https://www.intel.com/content/www/us/en/products/programmable/asic/easic-devices/diamond-mesa-soc-devices.html Patch status: Have changes: Patch 4, 5, 7, 12, 15 Other patches unchanged. Detail changelog can find in commit message. v2->v3: -------- Patch 4: - Adding helper function for getting endianness type. Patch 5: - Use BIT() macro for CLKMGR_INTER_*_MASK macro Patch 7: - Use BIT() and GENMASK() macro for all *MASK macro Patch 12: - Sorting header - Used prefix OPM_xxx - Simplify the code with do...while loop. - Created common function for processing handoff - Adding function of calibration data feedback to LPDDR4 controllers Patch 15: - Update comment for memory example code - Move all common dts settings for N5X from socfpga_n5x_socdk.dts to socfpga_n5x-u-boot.dtsi - Remove unused parameter "u-boot,boot0" History: -------- [v1] https://patchwork.ozlabs.org/project/uboot/cover/20210331143908.48211-1-elly.siew.chin.lim@intel.com/ [v2] https://patchwork.ozlabs.org/project/uboot/cover/20210430073814.193576-1-elly.siew.chin.lim@intel.com/ Siew Chin Lim (14): arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux function arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h arm: socfpga: Add base address for Intel N5X device drivers: clk: Add clock driver for Intel N5X device arm: socfpga: Get clock manager base address for Intel N5X device drivers: clk: Add memory clock driver for Intel N5X device arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.h arm: socfpga: Add clock manager for Intel N5X device arm: socfpga: Changed misc_s10.c to misc_soc64.c arm: socfpga: Add SPL for Intel N5X device board: intel: Add socdk board support for Intel N5X device arm: dts: Add base dtsi and devkit dts for Intel N5X device include: configs: Add Intel N5X device CONFIGs arm: socfpga: Enable Intel N5X device build Tien Fong Chee (3): arm: socfpga: Add handoff data support for Intel N5X device ddr: socfpga: Enable memory test on memory size less than 1GB ddr: altera: Add SDRAM driver for Intel N5X device arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_n5x-u-boot.dtsi | 175 ++ arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 67 + arch/arm/dts/socfpga_n5x_socdk.dts | 154 ++ arch/arm/mach-socfpga/Kconfig | 21 +- arch/arm/mach-socfpga/Makefile | 32 +- arch/arm/mach-socfpga/board.c | 17 +- arch/arm/mach-socfpga/clock_manager_n5x.c | 80 + .../{base_addr_s10.h => base_addr_soc64.h} | 11 +- .../mach-socfpga/include/mach/clock_manager.h | 3 + .../include/mach/clock_manager_agilex.h | 2 - .../include/mach/clock_manager_arria10.h | 1 - .../include/mach/clock_manager_gen5.h | 1 - .../include/mach/clock_manager_n5x.h | 12 + .../include/mach/clock_manager_s10.h | 1 - arch/arm/mach-socfpga/include/mach/firewall.h | 6 + .../mach-socfpga/include/mach/handoff_soc64.h | 38 +- .../include/mach/system_manager_soc64.h | 10 +- arch/arm/mach-socfpga/misc.c | 3 + .../mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 +- arch/arm/mach-socfpga/spl_n5x.c | 94 + arch/arm/mach-socfpga/system_manager_soc64.c | 18 +- arch/arm/mach-socfpga/wrap_handoff_soc64.c | 132 +- board/intel/n5x-socdk/MAINTAINERS | 7 + board/intel/n5x-socdk/Makefile | 7 + board/intel/n5x-socdk/socfpga.c | 7 + configs/socfpga_agilex_atf_defconfig | 2 +- ...tf_defconfig => socfpga_n5x_atf_defconfig} | 13 +- ...ex_atf_defconfig => socfpga_n5x_defconfig} | 29 +- ...tf_defconfig => socfpga_n5x_vab_defconfig} | 14 +- configs/socfpga_stratix10_atf_defconfig | 2 +- drivers/clk/altera/Makefile | 4 +- drivers/clk/altera/clk-mem-n5x.c | 136 + drivers/clk/altera/clk-mem-n5x.h | 84 + drivers/clk/altera/clk-n5x.c | 489 ++++ drivers/clk/altera/clk-n5x.h | 217 ++ drivers/ddr/altera/Makefile | 3 +- drivers/ddr/altera/sdram_n5x.c | 2298 +++++++++++++++++ drivers/ddr/altera/sdram_soc64.c | 94 +- drivers/ddr/altera/sdram_soc64.h | 1 + include/configs/socfpga_n5x_socdk.h | 45 + include/configs/socfpga_soc64_common.h | 2 +- include/dt-bindings/clock/n5x-clock.h | 71 + 43 files changed, 4296 insertions(+), 120 deletions(-) create mode 100644 arch/arm/dts/socfpga_n5x-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_n5x_socdk.dts create mode 100644 arch/arm/mach-socfpga/clock_manager_n5x.c rename arch/arm/mach-socfpga/include/mach/{base_addr_s10.h => base_addr_soc64.h} (85%) create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h rename arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} (100%) create mode 100644 arch/arm/mach-socfpga/spl_n5x.c create mode 100644 board/intel/n5x-socdk/MAINTAINERS create mode 100644 board/intel/n5x-socdk/Makefile create mode 100644 board/intel/n5x-socdk/socfpga.c copy configs/{socfpga_agilex_atf_defconfig => socfpga_n5x_atf_defconfig} (83%) copy configs/{socfpga_agilex_atf_defconfig => socfpga_n5x_defconfig} (63%) copy configs/{socfpga_agilex_atf_defconfig => socfpga_n5x_vab_defconfig} (82%) create mode 100644 drivers/clk/altera/clk-mem-n5x.c create mode 100644 drivers/clk/altera/clk-mem-n5x.h create mode 100644 drivers/clk/altera/clk-n5x.c create mode 100644 drivers/clk/altera/clk-n5x.h create mode 100644 drivers/ddr/altera/sdram_n5x.c create mode 100644 include/configs/socfpga_n5x_socdk.h create mode 100644 include/dt-bindings/clock/n5x-clock.h -- 2.19.0