From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65B5DC48BDF for ; Sun, 13 Jun 2021 08:51:26 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AA7866023F for ; Sun, 13 Jun 2021 08:51:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AA7866023F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 478AE82937; Sun, 13 Jun 2021 10:50:19 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 8C1A682893; Sun, 13 Jun 2021 10:49:42 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 11FBD81664 for ; Sun, 13 Jun 2021 10:49:21 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=elly.siew.chin.lim@intel.com IronPort-SDR: h9JEHHOKiIMf0myPXyJAI4n0L77YEOTSrfPL14Aa8ZTFqvOxdrrE6MH5CoEnJ+T8pJ16W8cKqy aWfpfcRaJJpA== X-IronPort-AV: E=McAfee;i="6200,9189,10013"; a="185398450" X-IronPort-AV: E=Sophos;i="5.83,270,1616482800"; d="scan'208";a="185398450" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2021 01:49:21 -0700 IronPort-SDR: XGdpUbp1T+q29zYa1M2PTA4aeW1+H53rsw02KGKuU3oERmE5Z8TmjlzHeT8i0WezQtmgJFrHWu SICUUf5UhCYw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,270,1616482800"; d="scan'208";a="441941656" Received: from pg-iccf0307.altera.com ([10.104.1.103]) by orsmga007.jf.intel.com with ESMTP; 13 Jun 2021 01:49:19 -0700 From: Siew Chin Lim To: u-boot@lists.denx.de Cc: Marek Vasut , Ley Foon Tan , Simon Goldschmidt , Tien Fong Chee , Dalon Westergreen , Simon Glass , Yau Wai Gan , Siew Chin Lim Subject: [v3 09/17] arm: socfpga: Add clock manager for Intel N5X device Date: Sun, 13 Jun 2021 16:48:44 +0800 Message-Id: <20210613084852.30868-10-elly.siew.chin.lim@intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20210613084852.30868-1-elly.siew.chin.lim@intel.com> References: <20210613084852.30868-1-elly.siew.chin.lim@intel.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Add clock manager for N5X. Signed-off-by: Siew Chin Lim --- ...k_manager_agilex.c => clock_manager_n5x.c} | 32 +++++++++---------- .../mach-socfpga/include/mach/clock_manager.h | 2 ++ .../include/mach/clock_manager_n5x.h | 12 +++++++ 3 files changed, 29 insertions(+), 17 deletions(-) copy arch/arm/mach-socfpga/{clock_manager_agilex.c => clock_manager_n5x.c} (64%) create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_n5x.c similarity index 64% copy from arch/arm/mach-socfpga/clock_manager_agilex.c copy to arch/arm/mach-socfpga/clock_manager_n5x.c index e035c09aae..4f098533e7 100644 --- a/arch/arm/mach-socfpga/clock_manager_agilex.c +++ b/arch/arm/mach-socfpga/clock_manager_n5x.c @@ -1,19 +1,18 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019 Intel Corporation + * Copyright (C) 2020-2021 Intel Corporation * */ -#include #include -#include -#include -#include #include #include #include #include -#include +#include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -25,7 +24,7 @@ static ulong cm_get_rate_dm(u32 id) int ret; ret = uclass_get_device_by_driver(UCLASS_CLK, - DM_DRIVER_GET(socfpga_agilex_clk), + DM_DRIVER_GET(socfpga_n5x_clk), &dev); if (ret) return 0; @@ -39,8 +38,7 @@ static ulong cm_get_rate_dm(u32 id) clk_free(&clk); - if ((rate == (unsigned long)-ENOSYS) || - (rate == (unsigned long)-ENXIO) || + if ((rate == (unsigned long)-ENXIO) || (rate == (unsigned long)-EIO)) { debug("%s id %u: clk_get_rate err: %ld\n", __func__, id, rate); @@ -57,26 +55,26 @@ static u32 cm_get_rate_dm_khz(u32 id) unsigned long cm_get_mpu_clk_hz(void) { - return cm_get_rate_dm(AGILEX_MPU_CLK); + return cm_get_rate_dm(N5X_MPU_CLK); } unsigned int cm_get_l4_sys_free_clk_hz(void) { - return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK); + return cm_get_rate_dm(N5X_L4_SYS_FREE_CLK); } void cm_print_clock_quick_summary(void) { printf("MPU %10d kHz\n", - cm_get_rate_dm_khz(AGILEX_MPU_CLK)); + cm_get_rate_dm_khz(N5X_MPU_CLK)); printf("L4 Main %8d kHz\n", - cm_get_rate_dm_khz(AGILEX_L4_MAIN_CLK)); + cm_get_rate_dm_khz(N5X_L4_MAIN_CLK)); printf("L4 sys free %8d kHz\n", - cm_get_rate_dm_khz(AGILEX_L4_SYS_FREE_CLK)); + cm_get_rate_dm_khz(N5X_L4_SYS_FREE_CLK)); printf("L4 MP %8d kHz\n", - cm_get_rate_dm_khz(AGILEX_L4_MP_CLK)); + cm_get_rate_dm_khz(N5X_L4_MP_CLK)); printf("L4 SP %8d kHz\n", - cm_get_rate_dm_khz(AGILEX_L4_SP_CLK)); + cm_get_rate_dm_khz(N5X_L4_SP_CLK)); printf("SDMMC %8d kHz\n", - cm_get_rate_dm_khz(AGILEX_SDMMC_CLK)); + cm_get_rate_dm_khz(N5X_SDMMC_CLK)); } diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index d0b172a30e..a8cb07a1c4 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -28,6 +28,8 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz); #include #elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) #include +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#include #endif #endif /* _CLOCK_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h b/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h new file mode 100644 index 0000000000..54615ae8f7 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2021 Intel Corporation + */ + +#ifndef _CLOCK_MANAGER_N5X_ +#define _CLOCK_MANAGER_N5X_ + +#include +#include "../../../../../drivers/clk/altera/clk-n5x.h" + +#endif /* _CLOCK_MANAGER_N5X_ */ -- 2.19.0