From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8FCFC48BCF for ; Sun, 13 Jun 2021 08:52:30 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2FCDE60FD8 for ; Sun, 13 Jun 2021 08:52:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2FCDE60FD8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 64B3282970; Sun, 13 Jun 2021 10:50:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id CF6F38293E; Sun, 13 Jun 2021 10:50:27 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 75B3F828A1 for ; Sun, 13 Jun 2021 10:49:41 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=elly.siew.chin.lim@intel.com IronPort-SDR: RvQysjMQJkTQWx09lj57dpAi3IAYgGQqUfXKzdmXkHWwwZ8dg1xCVOZNW6okkavJTdsulZXhHn wFN1y4TYKF8Q== X-IronPort-AV: E=McAfee;i="6200,9189,10013"; a="185398472" X-IronPort-AV: E=Sophos;i="5.83,270,1616482800"; d="scan'208";a="185398472" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2021 01:49:41 -0700 IronPort-SDR: w5j0udv6aXS2MtVYxgKkWN1hjofxEwEnwfm+P2xil1KXx1yVBuNbPZeeSteeI+njli2MpW+fbc Wu+9Dsx9sCnQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,270,1616482800"; d="scan'208";a="441941700" Received: from pg-iccf0307.altera.com ([10.104.1.103]) by orsmga007.jf.intel.com with ESMTP; 13 Jun 2021 01:49:37 -0700 From: Siew Chin Lim To: u-boot@lists.denx.de Cc: Marek Vasut , Ley Foon Tan , Simon Goldschmidt , Tien Fong Chee , Dalon Westergreen , Simon Glass , Yau Wai Gan , Siew Chin Lim Subject: [v3 16/17] include: configs: Add Intel N5X device CONFIGs Date: Sun, 13 Jun 2021 16:48:51 +0800 Message-Id: <20210613084852.30868-17-elly.siew.chin.lim@intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20210613084852.30868-1-elly.siew.chin.lim@intel.com> References: <20210613084852.30868-1-elly.siew.chin.lim@intel.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Add CONFIGs for N5X. Signed-off-by: Siew Chin Lim --- include/configs/socfpga_n5x_socdk.h | 45 +++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 include/configs/socfpga_n5x_socdk.h diff --git a/include/configs/socfpga_n5x_socdk.h b/include/configs/socfpga_n5x_socdk.h new file mode 100644 index 0000000000..c295e91e3d --- /dev/null +++ b/include/configs/socfpga_n5x_socdk.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020-2021 Intel Corporation + * + */ + +#ifndef __CONFIG_SOCFGPA_N5X_H__ +#define __CONFIG_SOCFGPA_N5X_H__ + +#include + +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bootfile=" CONFIG_BOOTFILE "\0" \ + "fdt_addr=1100000\0" \ + "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "booti ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootfile};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootm ${loadaddr}\0" \ + "mmcfitload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootfile}\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS";" \ + "booti ${loadaddr} - ${fdt_addr}\0" \ + "linux_qspi_enable=if sf probe; then " \ + "echo Enabling QSPI at Linux DTB...;" \ + "fdt addr ${fdt_addr}; fdt resize;" \ + "fdt set /soc/spi@ff8d2000 status okay;" \ + "if fdt set /soc/clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; then" \ + " else fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \ + " ${qspi_clock}; fi; fi\0" \ + "scriptaddr=0x02100000\0" \ + "scriptfile=u-boot.scr\0" \ + "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ + "then source ${scriptaddr}; fi\0" + +#endif /* __CONFIG_SOCFGPA_N5X_H__ */ -- 2.19.0