From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
To: Rick Chen <rick@andestech.com>, Leo <ycliang@andestech.com>
Cc: "Bin Meng" <bmeng.cn@gmail.com>,
"Sean Anderson" <seanga2@gmail.com>,
"Marek Behún" <marek.behun@nic.cz>,
"Green Wan" <green.wan@sifive.com>,
"Simon Glass" <sjg@chromium.org>,
"David Abdurachmanov" <david.abdurachmanov@sifive.com>,
"Dimitri John Ledkov" <dimitri.ledkov@canonical.com>,
"Ley Foon Tan" <ley.foon.tan@intel.com>,
"Chee Hong Ang" <chee.hong.ang@intel.com>,
"Sebastian Reichel" <sebastian.reichel@collabora.com>,
"Siew Chin Lim" <elly.siew.chin.lim@intel.com>,
u-boot@lists.denx.de,
"Heinrich Schuchardt" <heinrich.schuchardt@canonical.com>
Subject: [PATCH v6 1/4] riscv: add missing SBI extension definitions
Date: Sun, 12 Sep 2021 21:11:44 +0200 [thread overview]
Message-ID: <20210912191147.30051-2-heinrich.schuchardt@canonical.com> (raw)
In-Reply-To: <20210912191147.30051-1-heinrich.schuchardt@canonical.com>
Add the System Reset Extension and the Hart State Management Extension
definitions.
Add missing RFENCE Extension enum values.
The SBI 0.1 extension constants are needed for the sbi command. Remove
an #ifdef.
Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
v6:
no change
v5:
no change
v4:
no change
---
arch/riscv/include/asm/sbi.h | 39 ++++++++++++++++++++++++++++++++++--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 53ca316180..34a115afc3 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -12,7 +12,6 @@
#include <linux/types.h>
enum sbi_ext_id {
-#ifdef CONFIG_SBI_V01
SBI_EXT_0_1_SET_TIMER = 0x0,
SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
@@ -22,11 +21,12 @@ enum sbi_ext_id {
SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
SBI_EXT_0_1_SHUTDOWN = 0x8,
-#endif
SBI_EXT_BASE = 0x10,
SBI_EXT_TIME = 0x54494D45,
SBI_EXT_IPI = 0x735049,
SBI_EXT_RFENCE = 0x52464E43,
+ SBI_EXT_HSM = 0x48534D,
+ SBI_EXT_SRST = 0x53525354,
};
enum sbi_ext_base_fid {
@@ -51,6 +51,41 @@ enum sbi_ext_rfence_fid {
SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
+};
+
+enum sbi_ext_hsm_fid {
+ SBI_EXT_HSM_HART_START = 0,
+ SBI_EXT_HSM_HART_STOP,
+ SBI_EXT_HSM_HART_STATUS,
+ SBI_EXT_HSM_HART_SUSPEND,
+};
+
+enum sbi_hsm_hart_status {
+ SBI_HSM_HART_STATUS_STARTED = 0,
+ SBI_HSM_HART_STATUS_STOPPED,
+ SBI_HSM_HART_STATUS_START_PENDING,
+ SBI_HSM_HART_STATUS_STOP_PENDING,
+ SBI_HSM_HART_STATUS_SUSPEND_PENDING,
+ SBI_HSM_HART_STATUS_RESUME_PENDING,
+};
+
+enum sbi_ext_srst_fid {
+ SBI_EXT_SRST_RESET = 0,
+};
+
+enum sbi_srst_reset_type {
+ SBI_SRST_RESET_TYPE_SHUTDOWN = 0,
+ SBI_SRST_RESET_TYPE_COLD_REBOOT,
+ SBI_SRST_RESET_TYPE_WARM_REBOOT,
+};
+
+enum sbi_srst_reset_reason {
+ SBI_SRST_RESET_REASON_NONE = 0,
+ SBI_SRST_RESET_REASON_SYS_FAILURE,
};
#ifdef CONFIG_SBI_V01
--
2.32.0
next prev parent reply other threads:[~2021-09-12 19:12 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-12 19:11 [PATCH v6 0/4] riscv: enable SBI system reset Heinrich Schuchardt
2021-09-12 19:11 ` Heinrich Schuchardt [this message]
2021-09-12 19:11 ` [PATCH v6 2/4] cmd/sbi: use constants instead of numerical values Heinrich Schuchardt
2021-09-12 19:11 ` [PATCH v6 3/4] sysreset: provide SBI based sysreset driver Heinrich Schuchardt
2021-09-12 19:49 ` Samuel Holland
2021-09-12 19:11 ` [PATCH v6 4/4] configs: enable SYSRESET_SBI on qemu-riscvXX_smode_defconfig Heinrich Schuchardt
2021-09-14 9:02 ` Leo Liang
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