From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28DC4C433F5 for ; Mon, 13 Sep 2021 00:35:26 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 704E061029 for ; Mon, 13 Sep 2021 00:35:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 704E061029 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=konsulko.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D4C31839F3; Mon, 13 Sep 2021 02:35:15 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=konsulko.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 7E971839AD; Mon, 13 Sep 2021 02:32:56 +0200 (CEST) Received: from mail-qv1-f52.google.com (mail-qv1-f52.google.com [209.85.219.52]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 25F49839AE for ; Mon, 13 Sep 2021 02:32:46 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=konsulko.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tom.rini@gmail.com Received: by mail-qv1-f52.google.com with SMTP id jo30so67637qvb.3 for ; Sun, 12 Sep 2021 17:32:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=lAI55AA8OQQyizUL67oszyD5OAqtUT6bt+xcz/6ocRg=; b=taCJdnWHXNW+DYl5gsWyKeB9uBxfIJIqnY34WRoMHI5NlcNKIwG8JeqxoxXSay35m2 +OXRPB2B4L0s3uf+P67xtxKzcYjNDkwP6MZE++Win5fu7EcEdIGepXncfNUT7gCaej6T z4HLmiGaTeaXE7o3NW2BXuqDW6ntjjVV/t4e6sLZy/UG0UjglsguikTTEuno8LW0elx9 xqGA888KsmorDJl2fGieDkbMaC4xNtQIXZ/62WaNFem5iFSQtLf5OZebYDrYNEynNrGe UOH2oNx7yd6kJ/+F1+g1jj7cEaBzlRooDv+cBx/cMr9/ISCDM4szd81ICBUp8eo6hpTi BLlw== X-Gm-Message-State: AOAM533Mgx8/ZMWXh+nyKnVz43rQkSt4s7EIgXnQlXX51v6zi3Ev++A5 +vp/+bKHgQUlbDwnyLHGrqfjMR3m6g== X-Google-Smtp-Source: ABdhPJwL+r5CG4mNM4Gi8iZ7afchU2jhiX+kc9b2i7EXpvONW8Mh1EgjVB+tC7EFZJuME03q951Nvw== X-Received: by 2002:a05:6214:1809:: with SMTP id o9mr8395456qvw.58.1631493164671; Sun, 12 Sep 2021 17:32:44 -0700 (PDT) Received: from bill-the-cat.lan (2603-6081-7b01-cbda-0166-c2e8-bb10-efce.res6.spectrum.com. [2603:6081:7b01:cbda:166:c2e8:bb10:efce]) by smtp.gmail.com with ESMTPSA id x27sm3300211qtm.23.2021.09.12.17.32.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Sep 2021 17:32:44 -0700 (PDT) From: Tom Rini To: u-boot@lists.denx.de Subject: [PATCH 08/17] ti: keystone: Clean up or migrate some NAND related options. Date: Sun, 12 Sep 2021 20:32:24 -0400 Message-Id: <20210913003233.4125-8-trini@konsulko.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210913003233.4125-1-trini@konsulko.com> References: <20210913003233.4125-1-trini@konsulko.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean The COFNIG_KEYSTONE_RBL_NAND option is always enabled for the driver on keystone platforms, but not older davinci platforms. Use def_bool for the symbol. For CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE, it's only used within the driver and derived from another symbol, so remove CONFIG from the name. Finally, CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE is a bit more fixed. For now, use the value directly. Long term, as part of DM'ifying NAND, this should come from the device tree. Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/Kconfig | 4 ++++ drivers/mtd/nand/raw/davinci_nand.c | 12 ++++++------ include/configs/ti_armv7_keystone2.h | 2 -- 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index f7b1334ddb47..bb8cffcabcef 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -105,6 +105,10 @@ config NAND_DAVINCI Enable this driver for NAND flash controllers available in TI Davinci and Keystone2 platforms +config KEYSTONE_RBL_NAND + depends on ARCH_KEYSTONE + def_bool y + config NAND_DENALI bool select SYS_NAND_SELF_INIT diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c index 9ad3a57690e5..ef8e85a00212 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -347,9 +347,9 @@ static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = { }; #ifdef CONFIG_SYS_NAND_PAGE_2K -#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11 +#define KEYSTONE_NAND_MAX_RBL_PAGE (0x100000 >> 11) #elif defined(CONFIG_SYS_NAND_PAGE_4K) -#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12 +#define KEYSTONE_NAND_MAX_RBL_PAGE (0x100000 >> 12) #endif /** @@ -371,7 +371,7 @@ static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip, struct nand_ecclayout *saved_ecc_layout; /* save current ECC layout and assign Keystone RBL ECC layout */ - if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { + if (page < KEYSTONE_NAND_MAX_RBL_PAGE) { saved_ecc_layout = chip->ecc.layout; chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst; mtd->oobavail = chip->ecc.layout->oobavail; @@ -402,7 +402,7 @@ static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip, err: /* restore ECC layout */ - if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { + if (page < KEYSTONE_NAND_MAX_RBL_PAGE) { chip->ecc.layout = saved_ecc_layout; mtd->oobavail = saved_ecc_layout->oobavail; } @@ -433,7 +433,7 @@ static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip * struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout; /* save current ECC layout and assign Keystone RBL ECC layout */ - if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { + if (page < KEYSTONE_NAND_MAX_RBL_PAGE) { chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst; mtd->oobavail = chip->ecc.layout->oobavail; } @@ -463,7 +463,7 @@ static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip * } /* restore ECC layout */ - if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { + if (page < KEYSTONE_NAND_MAX_RBL_PAGE) { chip->ecc.layout = saved_ecc_layout; mtd->oobavail = saved_ecc_layout->oobavail; } diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index aa7b6ca9b809..512be7d328ea 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -119,8 +119,6 @@ /* EEPROM definitions */ /* NAND Configuration */ -#define CONFIG_KEYSTONE_RBL_NAND -#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET #define CONFIG_SYS_NAND_MASK_CLE 0x4000 #define CONFIG_SYS_NAND_MASK_ALE 0x2000 #define CONFIG_SYS_NAND_CS 2 -- 2.17.1