[PATCH 2/2] armv8/cache.S: Triple with single instruction

[PATCH 2/2] armv8/cache.S: Triple with single instruction

[Pierre-Clément Tosi]

Replace the current 2-instruction 2-step tripling code by a
corresponding single instruction leveraging ARMv8-A's "flexible second
operand as a register with optional shift". This has the added benefit
(albeit arguably negligible) of reducing the final code size.

Fix the comment as the tripled cache level is placed in x12, not x0.

Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
---
 arch/arm/cpu/armv8/cache.S | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index aabb3dff61..5051597f6f 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -80,8 +80,7 @@ ENTRY(__asm_dcache_all)
 	/* x15 <- return address */
 
 loop_level:
-	lsl	x12, x0, #1
-	add	x12, x12, x0		/* x0 <- tripled cache level */
+	add	x12, x0, x0, lsl #1	/* x12 <- tripled cache level */
 	lsr	x12, x10, x12
 	and	x12, x12, #7		/* x12 <- cache type */
 	cmp	x12, #2
-- 
2.33.0.259.gc128427fd7-goog


-- 
Pierre

Re: [PATCH 2/2] armv8/cache.S: Triple with single instruction

[Tom Rini]

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On Fri, Aug 27, 2021 at 06:04:10PM +0200, Pierre-Clément Tosi wrote:

> Replace the current 2-instruction 2-step tripling code by a
> corresponding single instruction leveraging ARMv8-A's "flexible second
> operand as a register with optional shift". This has the added benefit
> (albeit arguably negligible) of reducing the final code size.
> 
> Fix the comment as the tripled cache level is placed in x12, not x0.
> 
> Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>

Applied to u-boot/next, thanks!

-- 
Tom

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