From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BAC3C433F5 for ; Tue, 28 Sep 2021 11:41:23 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3D9A461139 for ; Tue, 28 Sep 2021 11:41:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 3D9A461139 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=ew.tq-group.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id ED6138312A; Tue, 28 Sep 2021 13:41:19 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=ew.tq-group.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=tq-group.com header.i=@tq-group.com header.b="VJxo+ZvQ"; dkim=pass (2048-bit key) header.d=tq-group.com header.i=@tq-group.com header.b="N5VCefHj"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 630FA80397; Tue, 28 Sep 2021 13:41:17 +0200 (CEST) Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4B48782DB7 for ; Tue, 28 Sep 2021 13:41:13 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=ew.tq-group.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=matthias.schiffer@ew.tq-group.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1632829273; x=1664365273; h=from:to:cc:subject:date:message-id; bh=7xREiFn3LAjhXv/hYg3yixQr9mFiNhLKcVrgyij8IhE=; b=VJxo+ZvQgPiV9r+qrcVM5C64pFrAWiW/OMlvQOmASCztqQ7NFVFSe/xJ iGrvMFG9QMKWjukIbNOrZv0spZknnuR3NJb6qTGzxJzFj+vkN18iCRMBR UeSRrqOBgJZdYnztckwdcvsiiUtjGutcbKomJisqbep+rt2BS+bOg4veD p4pOYcT/L3+slhX52AX5GTTsSt46Bycwtr0nEz7Z27rPMgg5jv4QOg9x8 JySGgWUw562sZLsauKLdvloaPKwiSabMGwS1zspPemJXK6f5HOgTV8OHK ubfL3Vx+i2mCgoJRE6HuPybCcKR2YL4Mhqu+nUrrQ1xvagd9c6GofMY+h g==; X-IronPort-AV: E=Sophos;i="5.85,329,1624312800"; d="scan'208";a="19749601" Received: from unknown (HELO tq-pgp-pr1.tq-net.de) ([192.168.6.15]) by mx1-pgp.tq-group.com with ESMTP; 28 Sep 2021 13:41:12 +0200 Received: from mx1.tq-group.com ([192.168.6.7]) by tq-pgp-pr1.tq-net.de (PGP Universal service); Tue, 28 Sep 2021 13:41:12 +0200 X-PGP-Universal: processed; by tq-pgp-pr1.tq-net.de on Tue, 28 Sep 2021 13:41:12 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1632829272; x=1664365272; h=from:to:cc:subject:date:message-id; bh=7xREiFn3LAjhXv/hYg3yixQr9mFiNhLKcVrgyij8IhE=; b=N5VCefHjiMUslzZ/JsKFOreCxwWoqLvUt54gYkcb+ySxg0tVTy6VmoNo QcOUMjK8zex24w7PZsQ9h7ACuRBOSYINlH9+W0Ypwrk6Jt6QftJnufF8D 5e2QClgtb/E8toOSBX4QmegXcOvbHMgehNcgLJ0setQbGjqmS7kdyrfzA ziO75gB++nlSJlgigG0c014h9GtENmeBjkC4lFgYW4oKZSYqgiSNH1dl8 5Uy6sQ3wnoN3aldzW7qctgIacbi9fAwHO5rcKW5s14c208lcwlZHl2IvP ZoANzrHdOW4RVzQR5mfre1X5tI6MOJChFaCvL36rC1LL1W6P7BX9ec6uC Q==; X-IronPort-AV: E=Sophos;i="5.85,329,1624312800"; d="scan'208";a="19749600" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 28 Sep 2021 13:41:12 +0200 Received: from schifferm-ubuntu4.tq-net.de (schifferm-ubuntu4.tq-net.de [10.121.48.12]) by vtuxmail01.tq-net.de (Postfix) with ESMTPA id E030C280065; Tue, 28 Sep 2021 13:41:11 +0200 (CEST) From: Matthias Schiffer To: Stefano Babic , Fabio Estevam Cc: "NXP i.MX U-Boot Team" , u-boot@lists.denx.de, Matthias Schiffer Subject: [PATCH] imx: mx7: spl: fix CONFIG_SPL_MAX_SIZE definition Date: Tue, 28 Sep 2021 13:40:52 +0200 Message-Id: <20210928114052.17178-1-matthias.schiffer@ew.tq-group.com> X-Mailer: git-send-email 2.17.1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean The CONFIG_SPL_MAX_SIZE definition did not account for all areas that are used by the boot ROM according to the manual, causing boot failures due to truncated SPL images when actually hitting this limit. Signed-off-by: Matthias Schiffer --- include/configs/imx7_spl.h | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/include/configs/imx7_spl.h b/include/configs/imx7_spl.h index 01d1cd83b23..128f612392f 100644 --- a/include/configs/imx7_spl.h +++ b/include/configs/imx7_spl.h @@ -18,15 +18,23 @@ * - Set the stack at the end of the free area section, at 0x00946BB8. * - The BOOT ROM loads what they consider the firmware image * which consists of a 4K header in front of us that contains the IVT, DCD - * and some padding thus 'our' max size is really 0x00946BB8 - 0x00911000. - * 64KB is more then enough for the SPL. + * and some padding. However, the manual also states that the ROM uses the + * OCRAM_EPCD and OCRAM_PXP areas for itself. While the SPL is free to use + * this range for stack and malloc, the SPL itself must fit below 0x920000, + * or the image will be truncated in at least some boot modes like USB SDP. + * Thus our max size is really 0x00920000 - 0x00912000. If necessary, + * CONFIG_SPL_TEXT_BASE could be moved to 0x00911000 to gain 4KB of space + * for the SPL, but 56KB should be more than enough for the SPL. */ -#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_MAX_SIZE 0xE000 #define CONFIG_SPL_STACK 0x00946BB8 /* - * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the - * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a - * boot media (given that boot media specific offset is configured properly). + * Pad SPL to 68KB (4KB header + 56KB max size + 8KB extra padding) + * The extra padding could be removed, but this value was used historically + * based on an incorrect CONFIG_SPL_MAX_SIZE definition. + * This allows to write the SPL/U-Boot combination generated with + * u-boot-with-spl.imx directly to a boot media (given that boot media specific + * offset is configured properly). */ #define CONFIG_SPL_PAD_TO 0x11000 -- 2.17.1