From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C197C433F5 for ; Thu, 30 Sep 2021 07:18:18 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7BD63615E5 for ; Thu, 30 Sep 2021 07:18:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 7BD63615E5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D816B8119C; Thu, 30 Sep 2021 09:18:14 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="keGeJjek"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id BE5F58169E; Thu, 30 Sep 2021 09:18:11 +0200 (CEST) Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7AC8D80F1A for ; Thu, 30 Sep 2021 09:18:06 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ilias.apalodimas@linaro.org Received: by mail-ed1-x533.google.com with SMTP id r18so18141607edv.12 for ; Thu, 30 Sep 2021 00:18:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=cKy1lQhrqHCbTGw8DJ5Fj0VBrqR7ZMTeU2AjfvpFWB4=; b=keGeJjekXe6d7TEUebov4VTCWQZks94NyMqyS9fJVM9Rv9jJITxhFvHdMGMAwpqDwO Htzo5wNnQswyN1EkB/1mkbWn4YEijNLVTCQJJyIPVjXYvxNgzPUrOcw0hcGE5elaJku4 kAh85qgOA05Wa/bzAETI68l5pIaP+ExSgKcs9+pAXTMByFtqg4kXvbv8trz3c8nsUHOX r8HAqUOQGc9JemC/vGSovI9D3KF4LpbUbZOQNohdP2BD5Yst0W2eQMjSF9UM3rxMHEs1 a1UmxDnGkdq0/B2Y5ipXRtyR3yLLCmG5xXe/spa8ZMggXgp+bw7mnDUSLa42ggTxnvxP pt8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=cKy1lQhrqHCbTGw8DJ5Fj0VBrqR7ZMTeU2AjfvpFWB4=; b=t33UvPOVLIwl/e3Rux+EjcnNTEf/04z5Prb7M7tdCxx6MG3MpstupczUk0Em5RymJ3 HP0qsnxJV79XC9FroUX5ZkSrNycaJ6kPfdgOqcg3kq1S9pbKEcEdtw60jDwE9JykL5fS kfOPkd+NRzEjGgfJK46R5dnW+L50ErVutelipyLDtLF1ca9RlYShPcDoTo5WFiXLW5Lc i5bVpdki+Dn7w+wVR11wVQHi30Q3yGwZfjTGwM7TKHAq9dAFNa4j+EHDW+uuEi6wg2Tz BIyAuyjxLRHFKuXzg7l4gIGJpMpnh8vIwm3Ab7M32UsdvUnS5X22jnq3vLTe9V7INaf0 HqAQ== X-Gm-Message-State: AOAM533S3QVUV9p6J498JFAp7m6J0WyQU0wyo7lbmpfwLgQjudl5LOHH EIrO83tBhdMyENZ+w1cathAHjA== X-Google-Smtp-Source: ABdhPJxRQKSzjokDXlcVPdAZFFI7qtkB+62pmxvH8i7LSkEf+F08VXYALqs/k8bgr8yU7WntTljWJw== X-Received: by 2002:a17:906:49d5:: with SMTP id w21mr5002566ejv.30.1632986284129; Thu, 30 Sep 2021 00:18:04 -0700 (PDT) Received: from apalos.home ([2a02:587:4672:866:2e56:dcff:fe9a:8f06]) by smtp.gmail.com with ESMTPSA id dj8sm1005173edb.53.2021.09.30.00.18.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 00:18:03 -0700 (PDT) From: Ilias Apalodimas To: trini@konsulko.com Cc: mark.kettenis@xs4all.nl, Ilias Apalodimas , Simon Glass , Bharat Gooty , Rayagonda Kokatanur , Rick Chen , Leo , Thomas Fitzsimmons , Bin Meng , =?UTF-8?q?Marek=20Beh=C3=BAn?= , Green Wan , Brad Kim , Heinrich Schuchardt , David Abdurachmanov , Dimitri John Ledkov , u-boot@lists.denx.de Subject: [PATCH 1/3 v3] riscv: Remove OF_PRIOR_STAGE from RISC-V boards Date: Thu, 30 Sep 2021 10:17:55 +0300 Message-Id: <20210930071800.443059-1-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.33.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean At some point back in 2018 prior_stage_fdt_address and OF_PRIOR_STAGE got introduced, in order to support a DTB handed over by an earlier stage boot loader. However we have another option in the Kconfig (OF_BOARD) which has identical semantics. On RISC-V some of the platforms pick up the DTB from a1 and copy it in their private gd_t. Apart from that they copy it to prior_stage_fdt_address, if the Kconfig option is selected, which is unnecessary. So let's switch the config option for those boards to OF_BOARD and define the required board_fdt_blob_setup() for them. Signed-off-by: Ilias Apalodimas Reviewed-by: Simon Glass --- Changes since v2: - Adjusted board_fdt_blob_setup() for ax25-ae350 to cover OF_BOARD cases Changes since v1: - Remove the sifive unleashed/unmatched changes, since they'll be handled arch/riscv/cpu/cpu.c | 3 --- arch/riscv/cpu/start.S | 5 ----- arch/riscv/dts/binman.dtsi | 6 +++--- board/AndesTech/ax25-ae350/ax25-ae350.c | 7 ++++++- board/emulation/qemu-riscv/qemu-riscv.c | 9 +++++++++ configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv32_spl_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- configs/ae350_rv64_spl_defconfig | 2 +- configs/qemu-riscv32_defconfig | 2 +- configs/qemu-riscv32_smode_defconfig | 2 +- configs/qemu-riscv32_spl_defconfig | 2 +- configs/qemu-riscv64_defconfig | 2 +- configs/qemu-riscv64_smode_defconfig | 2 +- configs/qemu-riscv64_spl_defconfig | 2 +- dts/Kconfig | 2 +- 16 files changed, 29 insertions(+), 23 deletions(-) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index c894ac10b536..e16f1df30254 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -16,9 +16,6 @@ * The variables here must be stored in the data section since they are used * before the bss section is available. */ -#ifdef CONFIG_OF_PRIOR_STAGE -phys_addr_t prior_stage_fdt_address __section(".data"); -#endif #ifndef CONFIG_XIP u32 hart_lottery __section(".data") = 0; diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 308b0a97a58f..76850ec9be2c 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -142,11 +142,6 @@ call_harts_early_init: bnez tp, secondary_hart_loop #endif -#ifdef CONFIG_OF_PRIOR_STAGE - la t0, prior_stage_fdt_address - SREG s1, 0(t0) -#endif - jal board_init_f_init_reserve SREG s1, GD_FIRMWARE_FDT_ADDR(gp) diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index d26cfdb78a9e..5757ef65ea4b 100644 --- a/arch/riscv/dts/binman.dtsi +++ b/arch/riscv/dts/binman.dtsi @@ -48,7 +48,7 @@ }; }; -#ifndef CONFIG_OF_PRIOR_STAGE +#ifndef CONFIG_OF_BOARD @fdt-SEQ { description = "NAME"; type = "flat_dt"; @@ -60,7 +60,7 @@ configurations { default = "conf-1"; -#ifndef CONFIG_OF_PRIOR_STAGE +#ifndef CONFIG_OF_BOARD @conf-SEQ { #else conf-1 { @@ -68,7 +68,7 @@ description = "NAME"; firmware = "opensbi"; loadables = "uboot"; -#ifndef CONFIG_OF_PRIOR_STAGE +#ifndef CONFIG_OF_BOARD fdt = "fdt-SEQ"; #endif }; diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index 81b0ee992372..6de91208258f 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c @@ -21,7 +21,6 @@ DECLARE_GLOBAL_DATA_PTR; -extern phys_addr_t prior_stage_fdt_address; /* * Miscellaneous platform dependent initializations */ @@ -57,7 +56,13 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) void *board_fdt_blob_setup(void) { +#if CONFIG_IS_ENABLED(OF_BOARD) + return (void *)gd->arch.firmware_fdt_addr; +#elif CONFIG_IS_ENABLED(OF_SEPARATE) return (void *)CONFIG_SYS_FDT_BASE; +#else + return NULL; +#endif } int smc_init(void) diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index dcfd3f20bee6..aa91ca91325c 100644 --- a/board/emulation/qemu-riscv/qemu-riscv.c +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -14,6 +14,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + int board_init(void) { /* @@ -69,3 +71,10 @@ int board_fit_config_name_match(const char *name) return 0; } #endif + +void *board_fdt_blob_setup(void) +{ + /* Stored the DTB address there during our init */ + return (void *)gd->arch.firmware_fdt_addr; +} + diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 4e7a1686a64d..8b6c0b8a4a0a 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -15,7 +15,7 @@ CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 34c6af6e7e17..a0fe9b9a71df 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -19,7 +19,7 @@ CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index 05eee371ac2f..cb23cbd3d95e 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -16,7 +16,7 @@ CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 9cd7848c92eb..9ad312505db3 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -20,7 +20,7 @@ CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index 8ac16cf4186e..6fe133c268d7 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -9,6 +9,6 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index 05eda439618f..c67e8206d1ab 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -10,6 +10,6 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index ee81e552724d..77e81fac3af7 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -12,6 +12,6 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_CMD_SBI=y # CONFIG_CMD_MII is not set -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index daf5d655d01f..90e87672aab0 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -10,6 +10,6 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index 4a6416e2540b..0a8393903368 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -13,6 +13,6 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index 429d4d814e65..a15e82dd3ee1 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -13,6 +13,6 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_CMD_SBI=y # CONFIG_CMD_MII is not set -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y diff --git a/dts/Kconfig b/dts/Kconfig index dabe0080c1ef..39270b47f9f0 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -107,7 +107,7 @@ config OF_EMBED Boards in the mainline U-Boot tree should not use it. config OF_BOARD - bool "Provided by the board at runtime" + bool "Provided by the board (e.g a previous loader) at runtime" depends on !SANDBOX help If this option is enabled, the device tree will be provided by -- 2.33.0