From: Pratyush Yadav <p.yadav@ti.com>
To: <tkuw584924@gmail.com>
Cc: <u-boot@lists.denx.de>, <jagan@amarulasolutions.com>,
<vigneshr@ti.com>, <Bacem.Daassi@infineon.com>,
Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Subject: Re: [PATCH v2] mtd: spi-nor-core: Add fixups for s25fs512s
Date: Thu, 30 Sep 2021 13:09:27 +0530 [thread overview]
Message-ID: <20210930073925.xg62yqfs46lnh7ea@ti.com> (raw)
In-Reply-To: <20210930053228.10760-1-Takahiro.Kuwano@infineon.com>
On 30/09/21 02:32PM, tkuw584924@gmail.com wrote:
> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
>
> The current S25FS512S support has following issues that need to be fixed.
>
> - Non-uniform sectors by factory default. The setting needs to be
> checked and assign erase hook as needed.
> - Page size is wrongly advertised in SFDP.
> - READ_1_1_2 (3Bh/3Ch), READ_1_1_4 (6Bh/6Ch), and PP_1_1_4 (32h/34h)
> are not supported.
> - Bank Address Register (BAR) is not supported.
>
> In addtion, volatile version of Quad Enable is used for safety.
>
> For future use, the fixups is assigned for S25FS-S family.
>
> The datasheet can be found in the following link.
> https://www.cypress.com/file/216376/download
>
> Tested on Xilinx Zynq-7000 FPGA board.
>
> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
next prev parent reply other threads:[~2021-09-30 7:39 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-30 5:32 [PATCH v2] mtd: spi-nor-core: Add fixups for s25fs512s tkuw584924
2021-09-30 7:39 ` Pratyush Yadav [this message]
2021-10-08 13:22 ` Jagan Teki
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