From: "Pali Rohár" <pali@kernel.org>
To: "Marek Behún" <kabel@kernel.org>
Cc: "Stefan Roese" <sr@denx.de>,
u-boot@lists.denx.de, "Marek Behún" <marek.behun@nic.cz>
Subject: Re: [PATCH u-boot-marvell v2 2/6] arm: a37xx: pci: Add support for accessing PCI Bridge on root bus
Date: Tue, 5 Oct 2021 23:55:48 +0200 [thread overview]
Message-ID: <20211005215548.vgmjux4iy2g3qhmg@pali> (raw)
In-Reply-To: <20210925225446.1872-3-kabel@kernel.org>
On Sunday 26 September 2021 00:54:42 Marek Behún wrote:
> @@ -355,20 +369,55 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
> enum pci_size_t size)
> {
> struct pcie_advk *pcie = dev_get_priv(bus);
> + int busno = PCI_BUS(bdf) - dev_seq(bus);
> int retry_count;
> bool allow_crs;
> + ulong data;
> uint reg;
> int ret;
>
> dev_dbg(pcie->dev, "PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
> PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
>
> - if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
> + if (!pcie_advk_addr_valid(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) {
> dev_dbg(pcie->dev, "- out of range\n");
> *valuep = pci_get_ff(size);
> return 0;
> }
>
> + /*
> + * The configuration space of the PCI Bridge on primary (local) bus is
> + * not accessible via PIO transfers like all other PCIe devices. PCI
> + * Bridge config registers are available directly in Aardvark memory
> + * space starting at offset zero. Moreover PCI Bridge registers in the
> + * range 0x10 - 0x34 are not available and register 0x38 (Expansion ROM
> + * Base Address) is at offset 0x30.
> + * We therefore read configuration space content of the primary PCI
> + * Bridge from our virtual cache.
> + */
> + if (busno == pcie->first_busno) {
> + if (offset >= 0x10 && offset < 0x34)
> + data = pcie->cfgcache[(offset - 0x10) / 4];
> + else if ((offset & ~3) == PCI_ROM_ADDRESS1)
> + data = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG);
> + else
> + data = advk_readl(pcie, offset & ~3);
> +
> + if ((offset & ~3) == (PCI_HEADER_TYPE & ~3)) {
> + /*
> + * Change Header Type of PCI Bridge device to Type 1
> + * (0x01, used by PCI Bridges) because hardwired value
> + * is Type 0 (0x00, used by Endpoint devices).
> + */
> + data &= ~0x00ff0000;
^^
There is a small mistake. Header Type is 7-bit value. Upper 8th bit
indicates if device is multifunction. So correct mask should be:
data &= ~0x007f0000;
> + data |= PCI_HEADER_TYPE_BRIDGE << 16;
> + }
> +
> + *valuep = pci_conv_32_to_size(data, offset, size);
> +
> + return 0;
> + }
> +
> /*
> * Returning fabricated CRS value (0xFFFF0001) by PCIe Root Complex to
> * OS is allowed only for 4-byte PCI_VENDOR_ID config read request and
next prev parent reply other threads:[~2021-10-05 21:56 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-25 22:54 [PATCH u-boot-marvell v2 0/6] A3720 PCIe enhancements Marek Behún
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 1/6] arm: a37xx: pci: Fix pcie_advk_link_up() Marek Behún
2021-10-08 6:20 ` Stefan Roese
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 2/6] arm: a37xx: pci: Add support for accessing PCI Bridge on root bus Marek Behún
2021-10-05 21:55 ` Pali Rohár [this message]
2021-10-08 6:20 ` Stefan Roese
2021-10-08 6:21 ` Stefan Roese
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 3/6] arm: a37xx: pci: Do not automatically enable bus mastering on PCI Bridge Marek Behún
2021-10-08 6:21 ` Stefan Roese
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 4/6] arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port Marek Behún
2021-10-08 6:21 ` Stefan Roese
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 5/6] arm: a37xx: pci: Cosmetic change Marek Behún
2021-10-08 6:21 ` Stefan Roese
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 6/6] arm: a37xx: pci: Update private structure documentation Marek Behún
2021-10-08 6:22 ` Stefan Roese
2021-10-08 9:18 ` [PATCH u-boot-marvell v2 0/6] A3720 PCIe enhancements Stefan Roese
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211005215548.vgmjux4iy2g3qhmg@pali \
--to=pali@kernel.org \
--cc=kabel@kernel.org \
--cc=marek.behun@nic.cz \
--cc=sr@denx.de \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).