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[95.249.225.173]) by smtp.gmail.com with ESMTPSA id h7sm1173932ede.19.2021.10.09.05.21.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Oct 2021 05:21:16 -0700 (PDT) From: Angelo Dureghello To: jagan@amarulasolutions.com, andre.przywara@arm.com, trini@konsulko.com Cc: u-boot@lists.denx.de, Angelo Dureghello Subject: [PATCH 2/2] sunxi: fix non working console on uart2 Date: Sat, 9 Oct 2021 14:18:59 +0200 Message-Id: <20211009121859.1384658-2-angelo.dureghello@timesys.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211009121859.1384658-1-angelo.dureghello@timesys.com> References: <20211009121859.1384658-1-angelo.dureghello@timesys.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Fix non working console on uart2, that seems releated to both Allwinner H2+ and H3. Signed-off-by: Angelo Dureghello --- arch/arm/include/asm/arch-sunxi/gpio.h | 1 + arch/arm/mach-sunxi/board.c | 10 +++++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 2969a530ae..21fcfd5638 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -150,6 +150,7 @@ enum sunxi_gpio_number { #define SUN7I_GPA_GMAC 5 #define SUN6I_GPA_SDC2 5 #define SUN6I_GPA_SDC3 4 +#define SUN8I_GPA_UART2 2 #define SUN8I_H3_GPA_UART0 2 #define SUN4I_GPB_PWM 2 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index adb63e93e7..623da744e2 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -145,10 +145,18 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) +#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) && \ + !defined(CONFIG_MACH_SUN8I_H2_PLUS) && \ + !defined(CONFIG_MACH_SUN8I_H3) sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) && \ + (defined(CONFIG_MACH_SUN8I_H2_PLUS) || \ + defined(CONFIG_MACH_SUN8I_H3)) + sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_GPA_UART2); + sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_GPA_UART2); + sunxi_gpio_set_pull(SUNXI_GPA(1), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); -- 2.32.0