From: Michael Walle <michael@walle.cc>
To: u-boot@lists.denx.de
Cc: Jagan Teki <jagan@amarulasolutions.com>,
Priyanka Jain <priyanka.jain@nxp.com>,
Vladimir Oltean <vladimir.oltean@nxp.com>,
Tom Rini <trini@konsulko.com>,
Peter Griffin <peter.griffin@linaro.org>,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
Michael Walle <michael@walle.cc>,
Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Subject: [PATCH v5 23/28] pci: layerscape: add official ls1028a binding support
Date: Wed, 13 Oct 2021 18:14:22 +0200 [thread overview]
Message-ID: <20211013161427.612033-24-michael@walle.cc> (raw)
In-Reply-To: <20211013161427.612033-1-michael@walle.cc>
The official bindind of the PCIe controller of the ls1028a has the
following compatible string:
compatible = "fsl,ls1028a-pcie";
Additionally, the resource names and count are different. Update the
driver to support this binding and change the entry in the ls1028a
device tree.
Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a.dtsi | 20 +++++------
drivers/pci/pcie_layerscape_rc.c | 61 +++++++++++++++++++++++---------
2 files changed, 53 insertions(+), 28 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index cc055e65e5..435b965d00 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -344,12 +344,10 @@
};
pcie1: pcie@3400000 {
- compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
- reg = <0x00 0x03400000 0x0 0x80000
- 0x00 0x03480000 0x0 0x40000 /* lut registers */
- 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
- 0x80 0x00000000 0x0 0x20000>; /* configuration space */
- reg-names = "dbi", "lut", "ctrl", "config";
+ compatible = "fsl,ls1028a-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -360,12 +358,10 @@
};
pcie2: pcie@3500000 {
- compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
- reg = <0x00 0x03500000 0x0 0x80000
- 0x00 0x03580000 0x0 0x40000 /* lut registers */
- 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
- 0x88 0x00000000 0x0 0x20000>; /* configuration space */
- reg-names = "dbi", "lut", "ctrl", "config";
+ compatible = "fsl,ls1028a-pcie";
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index f50d6ef653..217b420076 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -21,6 +21,12 @@
DECLARE_GLOBAL_DATA_PTR;
+struct ls_pcie_drvdata {
+ u32 lut_offset;
+ u32 ctrl_offset;
+ bool big_endian;
+};
+
static void ls_pcie_cfg0_set_busdev(struct ls_pcie_rc *pcie_rc, u32 busdev)
{
struct ls_pcie *pcie = pcie_rc->pcie;
@@ -243,6 +249,7 @@ static void ls_pcie_setup_ctrl(struct ls_pcie_rc *pcie_rc)
static int ls_pcie_probe(struct udevice *dev)
{
+ const struct ls_pcie_drvdata *drvdata = (void *)dev_get_driver_data(dev);
struct ls_pcie_rc *pcie_rc = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
@@ -260,8 +267,12 @@ static int ls_pcie_probe(struct udevice *dev)
pcie_rc->pcie = pcie;
+ /* try resource name of the official binding first */
ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
- "dbi", &pcie_rc->dbi_res);
+ "regs", &pcie_rc->dbi_res);
+ if (ret)
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "dbi", &pcie_rc->dbi_res);
if (ret) {
printf("ls-pcie: resource \"dbi\" not found\n");
return ret;
@@ -287,21 +298,29 @@ static int ls_pcie_probe(struct udevice *dev)
if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
return 0;
- ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
- "lut", &pcie_rc->lut_res);
- if (!ret)
- pcie->lut = map_physmem(pcie_rc->lut_res.start,
- fdt_resource_size(&pcie_rc->lut_res),
- MAP_NOCACHE);
+ if (drvdata) {
+ pcie->lut = pcie->dbi + drvdata->lut_offset;
+ } else {
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "lut", &pcie_rc->lut_res);
+ if (!ret)
+ pcie->lut = map_physmem(pcie_rc->lut_res.start,
+ fdt_resource_size(&pcie_rc->lut_res),
+ MAP_NOCACHE);
+ }
- ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
- "ctrl", &pcie_rc->ctrl_res);
- if (!ret)
- pcie->ctrl = map_physmem(pcie_rc->ctrl_res.start,
- fdt_resource_size(&pcie_rc->ctrl_res),
- MAP_NOCACHE);
- if (!pcie->ctrl)
- pcie->ctrl = pcie->lut;
+ if (drvdata) {
+ pcie->ctrl = pcie->lut + drvdata->ctrl_offset;
+ } else {
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "ctrl", &pcie_rc->ctrl_res);
+ if (!ret)
+ pcie->ctrl = map_physmem(pcie_rc->ctrl_res.start,
+ fdt_resource_size(&pcie_rc->ctrl_res),
+ MAP_NOCACHE);
+ if (!pcie->ctrl)
+ pcie->ctrl = pcie->lut;
+ }
if (!pcie->ctrl) {
printf("%s: NOT find CTRL\n", dev->name);
@@ -343,7 +362,10 @@ static int ls_pcie_probe(struct udevice *dev)
pcie_rc->cfg1 = pcie_rc->cfg0 +
fdt_resource_size(&pcie_rc->cfg_res) / 2;
- pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
+ if (drvdata)
+ pcie->big_endian = drvdata->big_endian;
+ else
+ pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
@@ -373,8 +395,15 @@ static const struct dm_pci_ops ls_pcie_ops = {
.write_config = ls_pcie_write_config,
};
+static const struct ls_pcie_drvdata ls1028a_drvdata = {
+ .lut_offset = 0x80000,
+ .ctrl_offset = 0x40000,
+ .big_endian = false,
+};
+
static const struct udevice_id ls_pcie_ids[] = {
{ .compatible = "fsl,ls-pcie" },
+ { .compatible = "fsl,ls1028a-pcie", .data = (ulong)&ls1028a_drvdata },
{ }
};
--
2.30.2
next prev parent reply other threads:[~2021-10-13 16:19 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-13 16:13 [PATCH v5 00/28] arm: dts: ls1028a: sync device tree with linux Michael Walle
2021-10-13 16:14 ` [PATCH v5 01/28] armv8: ls1028a: use the official compatible string for the GPU Michael Walle
2021-10-13 16:14 ` [PATCH v5 02/28] arm: dts: ls1028a: remove /memory node Michael Walle
2021-10-13 16:14 ` [PATCH v5 03/28] arm: dts: ls1028a-{rdb, qds}: remove dm-pre-reloc property Michael Walle
2021-10-13 16:14 ` [PATCH v5 04/28] arm: dts: ls1028a: add an empty /soc Michael Walle
2021-10-13 16:14 ` [PATCH v5 05/28] arm: dts: ls1028a: move the clockgen node into /soc Michael Walle
2021-10-13 16:14 ` [PATCH v5 06/28] arm: dts: ls1028a: move I2C controller nodes " Michael Walle
2021-10-13 16:14 ` [PATCH v5 07/28] arm: dts: ls1028a: move the FlexSPI controller node Michael Walle
2021-10-13 16:14 ` [PATCH v5 08/28] arm: dts: ls1028a: move the SPI and eSDHC controller nodes into /soc Michael Walle
2021-10-13 16:14 ` [PATCH v5 09/28] arm: dts: ls1028a: move the UART " Michael Walle
2021-10-13 16:14 ` [PATCH v5 10/28] arm: dts: ls1028a: move the low-power UART " Michael Walle
2021-10-13 16:14 ` [PATCH v5 11/28] arm: dts: ls1028a: move the GPIO controller " Michael Walle
2021-10-13 16:14 ` [PATCH v5 12/28] arm: dts: ls1028a: move SATA and USB " Michael Walle
2021-10-13 16:14 ` [PATCH v5 13/28] arm: dts: ls1028a: move the PCIe " Michael Walle
2021-10-13 16:14 ` [PATCH v5 14/28] arm: dts: ls1028a: move the watchdog node " Michael Walle
2021-10-13 16:14 ` [PATCH v5 15/28] arm: dts: ls1028a: move the iRC node and its devices " Michael Walle
2021-10-13 16:14 ` [PATCH v5 16/28] arm: dts: ls1028a: update the labels Michael Walle
2021-10-13 16:14 ` [PATCH v5 17/28] watchdog: sp805_wdt: use correct compatible string Michael Walle
2021-10-13 16:14 ` [PATCH v5 18/28] spi: fsl_dspi: add new compatible fsl, ls1021a-v1.0-dspi Michael Walle
2021-10-13 16:14 ` [PATCH v5 19/28] spi: fsl_dspi: rename num-cs to spi-num-chipselects Michael Walle
2021-10-13 16:14 ` [PATCH v5 20/28] serial: lpuart: add new compatible fsl, ls1028a-lpuart Michael Walle
2021-10-13 16:14 ` [PATCH v5 21/28] scsi: ceva: rename the resource name to match the linux kernel one Michael Walle
2021-10-13 16:14 ` [PATCH v5 22/28] usb: xhci: fsl: add new compatible fsl,ls1028a-dwc3 Michael Walle
2021-10-13 16:14 ` Michael Walle [this message]
2021-10-31 13:26 ` [PATCH v5 23/28] pci: layerscape: add official ls1028a binding support Z.Q. Hou
2021-10-13 16:14 ` [PATCH v5 24/28] arm: dts: ls1028a: remove num-lanes in the PCIe controller nodes Michael Walle
2021-10-13 16:14 ` [PATCH v5 25/28] arm: dts: ls1028a: move the PCI I/O window to match Michael Walle
2021-10-13 16:14 ` [PATCH v5 26/28] arm: dts: ls1028a: disable the PCIe controller by default Michael Walle
2021-10-13 16:14 ` [PATCH v5 27/28] arm: dts: ls1028a: sync the fsl-ls1028a.dtsi with linux Michael Walle
2021-10-13 16:14 ` [PATCH v5 28/28] arm: dts: sl28: sync dtbs Michael Walle
2021-11-10 8:47 ` Michael Walle
2021-11-10 21:33 ` Tom Rini
2021-11-11 4:46 ` Priyanka Jain (OSS)
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