From: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
To: sbabic@denx.de, festevam@gmail.com
Cc: u-boot@lists.denx.de, Ye Li <ye.li@nxp.com>, Peng Fan <peng.fan@nxp.com>
Subject: [PATCH 05/20] imx8ulp: clock: Add MIPI DSI clock and DCNano clock
Date: Fri, 29 Oct 2021 09:46:19 +0800 [thread overview]
Message-ID: <20211029014634.20949-6-peng.fan@oss.nxp.com> (raw)
In-Reply-To: <20211029014634.20949-1-peng.fan@oss.nxp.com>
From: Ye Li <ye.li@nxp.com>
Add the DSI clock enable and disable with PCC reset used.
Add the LCD pixel clock calculation and configuration for DCNano
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx8ulp/clock.h | 2 +
arch/arm/mach-imx/imx8ulp/clock.c | 73 +++++++++++++++++++++++
2 files changed, 75 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8ulp/clock.h b/arch/arm/include/asm/arch-imx8ulp/clock.h
index 58e3356e32..24322f3ab2 100644
--- a/arch/arm/include/asm/arch-imx8ulp/clock.h
+++ b/arch/arm/include/asm/arch-imx8ulp/clock.h
@@ -38,4 +38,6 @@ void init_clk_ddr(void);
int set_ddr_clk(u32 phy_freq_mhz);
void clock_init(void);
void cgc1_enet_stamp_sel(u32 clk_src);
+void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz);
+void enable_mipi_dsi_clk(unsigned char enable);
#endif
diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index 2beacbceb0..02e90f7856 100644
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -317,6 +317,79 @@ int enable_usb_pll(ulong usb_phy_base)
return 0;
}
+void enable_mipi_dsi_clk(unsigned char enable)
+{
+ if (enable) {
+ pcc_clock_enable(5, DSI_PCC5_SLOT, false);
+ pcc_clock_sel(5, DSI_PCC5_SLOT, PLL4_PFD3_DIV2);
+ pcc_clock_div_config(5, DSI_PCC5_SLOT, 0, 6);
+ pcc_clock_enable(5, DSI_PCC5_SLOT, true);
+ pcc_reset_peripheral(5, DSI_PCC5_SLOT, false);
+ } else {
+ pcc_clock_enable(5, DSI_PCC5_SLOT, false);
+ pcc_reset_peripheral(5, DSI_PCC5_SLOT, true);
+ }
+}
+
+void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz)
+{
+ u8 pcd, best_pcd = 0;
+ u32 frac, rate, parent_rate, pfd, div;
+ u32 best_pfd = 0, best_frac = 0, best = 0, best_div = 0;
+ u32 pll4_rate;
+
+ pcc_clock_enable(5, DCNANO_PCC5_SLOT, false);
+
+ pll4_rate = cgc_clk_get_rate(PLL4);
+ pll4_rate = pll4_rate / 1000; /* Change to khz*/
+
+ debug("PLL4 rate %ukhz\n", pll4_rate);
+
+ for (pfd = 12; pfd <= 35; pfd++) {
+ parent_rate = pll4_rate;
+ parent_rate = parent_rate * 18 / pfd;
+
+ for (div = 1; div <= 64; div++) {
+ parent_rate = parent_rate / div;
+
+ for (pcd = 0; pcd < 8; pcd++) {
+ for (frac = 0; frac < 2; frac++) {
+ if (pcd == 0 && frac == 1)
+ continue;
+
+ rate = parent_rate * (frac + 1) / (pcd + 1);
+ if (rate > freq_in_khz)
+ continue;
+
+ if (best == 0 || rate > best) {
+ best = rate;
+ best_pfd = pfd;
+ best_frac = frac;
+ best_pcd = pcd;
+ best_div = div;
+ }
+ }
+ }
+ }
+ }
+
+ if (best == 0) {
+ printf("Can't find parent clock for LCDIF, target freq: %u\n", freq_in_khz);
+ return;
+ }
+
+ debug("LCD target rate %ukhz, best rate %ukhz, frac %u, pcd %u, best_pfd %u, best_div %u\n",
+ freq_in_khz, best, best_frac, best_pcd, best_pfd, best_div);
+
+ cgc2_pll4_pfd_config(PLL4_PFD0, best_pfd);
+ cgc2_pll4_pfddiv_config(PLL4_PFD0_DIV1, best_div - 1);
+
+ pcc_clock_sel(5, DCNANO_PCC5_SLOT, PLL4_PFD0_DIV1);
+ pcc_clock_div_config(5, DCNANO_PCC5_SLOT, best_frac, best_pcd + 1);
+ pcc_clock_enable(5, DCNANO_PCC5_SLOT, true);
+ pcc_reset_peripheral(5, DCNANO_PCC5_SLOT, false);
+}
+
u32 mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
--
2.30.0
next prev parent reply other threads:[~2021-10-29 1:11 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-29 1:46 [PATCH 00/20] i.MX8ULP misc update Peng Fan (OSS)
2021-10-29 1:46 ` [PATCH 01/20] imx8ulp: soc: Check the DBD_EN fuse before setting RDC Peng Fan (OSS)
2022-02-05 16:42 ` sbabic
2021-10-29 1:46 ` [PATCH 02/20] arm: imx8ulp: Allocate LPAV resources to AP domain Peng Fan (OSS)
2022-02-05 16:39 ` sbabic
2021-10-29 1:46 ` [PATCH 03/20] imx8ulp: assign PXP/HIFI4/EPDC to APD domain Peng Fan (OSS)
2022-02-05 16:43 ` sbabic
2021-10-29 1:46 ` [PATCH 04/20] imx8ulp: clock: Support LPAV clocks in cgc and pcc Peng Fan (OSS)
2022-02-05 16:39 ` sbabic
2021-10-29 1:46 ` Peng Fan (OSS) [this message]
2022-02-05 16:44 ` [PATCH 05/20] imx8ulp: clock: Add MIPI DSI clock and DCNano clock sbabic
2021-10-29 1:46 ` [PATCH 06/20] imx8ulp: rdc: allow A35 access flexspi0 mem Peng Fan (OSS)
2022-02-05 16:43 ` sbabic
2021-10-29 1:46 ` [PATCH 07/20] imx8ulp_evk: Control LPI2C0 PCA6416 and TPM0 for display Peng Fan (OSS)
2022-02-05 16:43 ` sbabic
2021-10-29 1:46 ` [PATCH 08/20] imx8ulp: Set DCNANO read QoS on NIC_LPAV to highest Peng Fan (OSS)
2022-02-05 16:39 ` sbabic
2021-10-29 1:46 ` [PATCH 09/20] imx8ulp: Fix DCNANO QoS setting Peng Fan (OSS)
2022-02-05 16:42 ` sbabic
2021-10-29 1:46 ` [PATCH 10/20] imx8ulp: Remove freescale name from CPU revision Peng Fan (OSS)
2022-02-05 16:41 ` sbabic
2021-10-29 1:46 ` [PATCH 11/20] imx8ulp: Workaround LPOSC_TRIM fuse load issue Peng Fan (OSS)
2022-02-05 16:40 ` sbabic
2021-10-29 1:46 ` [PATCH 12/20] imx8ulp: clock: Reset DDR controller before clock enable Peng Fan (OSS)
2022-02-05 16:41 ` sbabic
2021-10-29 1:46 ` [PATCH 13/20] imx8ulp: clock: Support to reset DCNano and MIPI DSI Peng Fan (OSS)
2022-02-05 16:41 ` sbabic
2021-10-29 1:46 ` [PATCH 14/20] imx8ulp: Update ethernet mac to get from fuse Peng Fan (OSS)
2022-02-05 16:40 ` sbabic
2021-10-29 1:46 ` [PATCH 15/20] imx8ulp: clock: Support to enable/disable the ADC1 clock Peng Fan (OSS)
2022-02-05 16:43 ` sbabic
2021-10-29 1:46 ` [PATCH 16/20] imx8ulp: clock: Handle the DDRLOCKED when setting DDR clock Peng Fan (OSS)
2022-02-05 16:43 ` sbabic
2021-10-29 1:46 ` [PATCH 18/20] imx8ulp: implement to obtain the SoC current temperature Peng Fan (OSS)
2022-02-05 16:42 ` sbabic
2021-10-29 1:46 ` [PATCH 19/20] imx8ulp:ddr: saving the dram config timing data into sram Peng Fan (OSS)
2022-02-05 16:40 ` sbabic
2021-10-29 1:46 ` [PATCH 20/20] imx8ulp: ddr: Fix DDR frequency request issue Peng Fan (OSS)
2022-02-05 16:40 ` sbabic
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