On Mon, Sep 13, 2021 at 01:59:11PM +0800, nicholas_zheng@outlook.com wrote:

> From: weichangzheng <nicholas_zheng@outlook.com>
> 
> This adds platform code and the device tree for the Phytium Pomelo Board.
> The initial support comprises the UART and the PCIE.
> 
> Signed-off-by: weichangzheng <nicholas_zheng@outlook.com>
> Changes since v1:
>         updated to DT
> Changes since v2:
>         Modify some explicit types and macro
> Changes since v3:
> 	Modify some SDRAM related macro definitions and distro_bootcmd
> Changes since v4:
> 	Modify distro_bootcmd
> Changes since v5:
> 	Modify the CPU node description of the DT
> Changes since v6:
> 	Modify  DT
> ---
[snip]
> diff --git a/arch/arm/dts/phytium-pomelo.dts b/arch/arm/dts/phytium-pomelo.dts
> new file mode 100644
> index 0000000000..4ed97e090d
> --- /dev/null
> +++ b/arch/arm/dts/phytium-pomelo.dts
> @@ -0,0 +1,118 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * dts file for Phytium Pomelo board
> + * Copyright (C) 2021, Phytium Ltd.
> + * lixinde         <lixinde@phytium.com.cn>
> + * weichangzheng   <weichangzheng@phytium.com.cn>
> + */
> +/dts-v1/;
> +
> +/ {
> +	model = "Phytium Pomelo";
> +	compatible = "phytium,d2000";
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	cpus {
> +		#address-cells = <0x2>;
> +		#size-cells = <0x0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x0>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x1>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu2: cpu@100 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x100>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu3: cpu@101 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x101>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu4: cpu@200 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x200>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu5: cpu@201 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x201>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu6: cpu@300 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x300>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu7: cpu@301 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x301>;
> +			enable-method = "psci";
> +		};
> +	};
> +
> +	clocks {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		sysclk_48mhz: clk48mhz {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0x0>;
> +			clock-frequency = <48000000>;
> +			clock-output-names = "sysclk_48mhz";
> +		};
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		uart0: serial@28001000 {
> +			compatible = "arm,pl011";
> +			reg = <0x0 0x28001000 0x0 0x1000>;
> +			clocks = <&sysclk_48mhz>;
> +		};
> +
> +		pcie@40000000 {
> +			compatible = "pci-host-ecam-generic";
> +			device_type = "pci";
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			reg = <0x0 0x40000000 0x0 0x10000000>;
> +			bus-range = <0x0 0xff>;
> +			ranges = <0x01000000 0x00 0x00000000 0x0  0x50000000 0x0  0x00F00000>,
> +			 <0x02000000 0x00 0x58000000 0x0  0x58000000 0x0  0x28000000>,
> +			 <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10  0x00000000>;
> +		};
> +	};
> +};

Any further device tree comments, Rob?  Thanks!

-- 
Tom