From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BAF24C433EF for ; Fri, 26 Nov 2021 10:45:52 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 07FAA8378D; Fri, 26 Nov 2021 11:44:45 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="LwI7MBab"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id ADAB08376C; Fri, 26 Nov 2021 11:44:10 +0100 (CET) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6AA7D83781 for ; Fri, 26 Nov 2021 11:43:48 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: by mail.kernel.org (Postfix) with ESMTPSA id 32145601FF; Fri, 26 Nov 2021 10:43:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637923425; bh=nJxZby4mqF/bY0UBq/5uGCvzV0IQ/meXFEMVW8gYecc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LwI7MBabEE1z6FPfJ58cU/1kx3aGHflxf2XT8t0PmQI6ivR3A3tPCcM5/hQm+Z6Cd h3Iaq5sP1f7o1zzXI6F+iB3C3/gdVHVo1x9YoQ9bB/Z4mJWeb/ibGgQnPX64dwGfrV uasE08l2VSKBqVB8bmE/FgcxbbWJEOyNltw7IErWoBHV75SFynqmjYKoJ2OLxoX3BB qjxmBVK7lpjpiqrhq381Q9zf6js9e5QAIqBd1UWeLqlxm8/W2Y1SZY4WeKydWSNcCM DfQsS3lKKT++0O5Tg1hNWrnxKw7lE5TrIbL4oDUNa/PpeEGC2Lkevw9uoOGYTr2PFc dBy6sS6EYc8oQ== Received: by pali.im (Postfix) id E8E745B2; Fri, 26 Nov 2021 11:43:44 +0100 (CET) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Stefan Roese , Simon Glass , Bin Meng , Ryder Lee , Weijie Gao , Chunfeng Yun , GSS_MTK_Uboot_upstream Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-next 08/12] pci: mediatek: Use PCI_CONF1_EXT_ADDRESS() macro Date: Fri, 26 Nov 2021 11:42:48 +0100 Message-Id: <20211126104252.5443-9-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211126104252.5443-1-pali@kernel.org> References: <20211126104252.5443-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.37 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean PCI mediatek driver uses extended format of Config Address for PCI Configuration Mechanism #1 but with cleared Enable bit. So use new U-Boot macro PCI_CONF1_EXT_ADDRESS() with clearing PCI_CONF1_ENABLE bit and remove old custom driver address macros. Signed-off-by: Pali Rohár --- drivers/pci/pcie_mediatek.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/pci/pcie_mediatek.c b/drivers/pci/pcie_mediatek.c index f5556713878f..051a3bc96935 100644 --- a/drivers/pci/pcie_mediatek.c +++ b/drivers/pci/pcie_mediatek.c @@ -41,10 +41,6 @@ #define PCIE_BAR_ENABLE BIT(0) #define PCIE_REVISION_ID BIT(0) #define PCIE_CLASS_CODE (0x60400 << 8) -#define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \ - ((((regn) >> 8) & GENMASK(3, 0)) << 24)) -#define PCIE_CONF_ADDR(regn, bdf) \ - (PCIE_CONF_REG(regn) | (bdf)) /* MediaTek specific configuration registers */ #define PCIE_FTS_NUM 0x70c @@ -147,8 +143,11 @@ static int mtk_pcie_config_address(const struct udevice *udev, pci_dev_t bdf, uint offset, void **paddress) { struct mtk_pcie *pcie = dev_get_priv(udev); + u32 val; - writel(PCIE_CONF_ADDR(offset, bdf), pcie->base + PCIE_CFG_ADDR); + val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), + PCI_FUNC(bdf), offset) & ~PCI_CONF1_ENABLE; + writel(val, pcie->base + PCIE_CFG_ADDR); *paddress = pcie->base + PCIE_CFG_DATA + (offset & 3); return 0; @@ -330,7 +329,6 @@ static void mtk_pcie_port_free(struct mtk_pcie_port *port) static int mtk_pcie_startup_port(struct mtk_pcie_port *port) { struct mtk_pcie *pcie = port->pcie; - u32 slot = PCI_DEV(port->slot << 11); u32 val; int err; @@ -357,13 +355,14 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port) writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS); /* configure FC credit */ - writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, slot), - pcie->base + PCIE_CFG_ADDR); + val = PCI_CONF1_EXT_ADDRESS(0, port->slot, 0, PCIE_FC_CREDIT) & ~PCI_CONF1_ENABLE; + writel(val, pcie->base + PCIE_CFG_ADDR); clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FC_CREDIT_MASK, PCIE_FC_CREDIT_VAL(0x806c)); /* configure RC FTS number to 250 when it leaves L0s */ - writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, slot), pcie->base + PCIE_CFG_ADDR); + val = PCI_CONF1_EXT_ADDRESS(0, port->slot, 0, PCIE_FTS_NUM) & ~PCI_CONF1_ENABLE; + writel(val, pcie->base + PCIE_CFG_ADDR); clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FTS_NUM_MASK, PCIE_FTS_NUM_L0(0x50)); -- 2.20.1