From: Daniel Wagenknecht <dwagenk@mailbox.org>
To: u-boot@lists.denx.de
Cc: Daniel Wagenknecht <dwagenk@mailbox.org>,
Andre Przywara <andre.przywara@arm.com>,
Jagan Teki <jagan@amarulasolutions.com>
Subject: [PATCH 1/1] sunxi: SPI: fix pinmuxing for Allwinner H6 SoCs
Date: Sun, 12 Dec 2021 20:29:06 +0100 [thread overview]
Message-ID: <20211212192906.946068-1-dwagenk@mailbox.org> (raw)
The driver for SPI0 on Allwinner H6 SoCs did not use the correct define
SUN50I_GPC_SPI0 for the pin function, but one for a different Allwinner
SoC series.
Fix the conditionals to use the correct define for H6 SoCs. This matches
the conditional logic in the SPL spi driver.
Tested by probing the spi-flash on a pine64_h64-model-b board with
adapted device-tree (disable mmc2, enable spi0).
Signed-off-by: Daniel Wagenknecht <dwagenk@mailbox.org>
---
drivers/spi/spi-sunxi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index bc2f544e86..6a8ee8d542 100644
--- a/drivers/spi/spi-sunxi.c
+++ b/drivers/spi/spi-sunxi.c
@@ -249,7 +249,8 @@ static int sun4i_spi_parse_pins(struct udevice *dev)
if (pin < 0)
break;
- if (IS_ENABLED(CONFIG_MACH_SUN50I))
+ if (IS_ENABLED(CONFIG_MACH_SUN50I) ||
+ IS_ENABLED(CONFIG_MACH_SUN50I_H6))
sunxi_gpio_set_cfgpin(pin, SUN50I_GPC_SPI0);
else
sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0);
--
2.31.1
next reply other threads:[~2021-12-12 19:31 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-12 19:29 Daniel Wagenknecht [this message]
2021-12-14 23:54 ` [PATCH 1/1] sunxi: SPI: fix pinmuxing for Allwinner H6 SoCs Andre Przywara
2021-12-16 19:38 ` Daniel Wagenknecht
2021-12-16 19:42 ` [PATCH v2] " Daniel Wagenknecht
2021-12-14 20:53 [PATCH 0/1] fix SPI " Daniel Wagenknecht
2021-12-14 20:53 ` [PATCH 1/1] sunxi: SPI: fix " Daniel Wagenknecht
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