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Fri, 17 Dec 2021 15:21:03 +0000 (UTC) Received: from midas.localdomain (S0106788a2041785e.gv.shawcable.net [24.108.106.191]) by node.akkea.ca (Postfix) with ESMTPSA id E45EE4E2006; Fri, 17 Dec 2021 15:21:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akkea.ca; s=mail; t=1639754463; bh=Aklg4gL8t8oYyvaOkYXz4yorv2k5NOulbbBSaHTcmIA=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=XRQTvq+Ujc17DkyGYrS5d9OnkgvFn+puGv58O1qwiEg5L4ylBMB7QlzBcaRtJZDGG hqLPzzMY0ZzX6d14CMqZ4PWKbufStnFtzO7vbWHhldXKwMnxyKYBI+jYgl76nOkCm5 dmTrDRV689RJak0mozZEPrN7dx8u6TaeSYgpplcA= From: Angus Ainslie To: u-boot@lists.denx.de, "NXP i.MX U-Boot Team" Cc: Stefano Babic , Fabio Estevam , Peng Fan , Angus Ainslie , Marek Vasut , Ye Li , Alice Guo , Patrick Wildt , Simon Glass , Frieder Schrempf , =?UTF-8?q?Marek=20Beh=C3=BAn?= , "Ying-Chun Liu (PaulLiu)" , kernel@puri.sm Subject: [PATCH 1/3] imx8m: clock_imx8mq: Add the ecspi clocks Date: Fri, 17 Dec 2021 07:20:38 -0800 Message-Id: <20211217152040.324803-2-angus@akkea.ca> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211217152040.324803-1-angus@akkea.ca> References: <20211217152040.324803-1-angus@akkea.ca> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Enable the clocks for spi buses 1 through 3 Signed-off-by: Angus Ainslie --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 9 +++++ arch/arm/mach-imx/imx8m/clock_imx8mq.c | 38 ++++++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index b800da13a1..8cb499d3a3 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -94,6 +94,15 @@ #define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1) #define SRC_DDR1_RCR_PRESET_N_MASK BIT(0) +#define IMX_CSPI1_BASE 0x30820000 +#define IMX_CSPI2_BASE 0x30830000 +#define IMX_CSPI3_BASE 0x30840000 + +#define MXC_SPI_BASE_ADDRESSES \ + IMX_CSPI1_BASE, \ + IMX_CSPI2_BASE, \ + IMX_CSPI3_BASE + struct iomuxc_gpr_base_regs { u32 gpr[47]; }; diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 60e2218a3c..834a7bfa01 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -505,6 +505,31 @@ int set_clk_qspi(void) return 0; } +int set_clk_ecspi(int sel) +{ + int clk = ECSPI1_CLK_ROOT; + + switch (sel) { + case 1: + clk = ECSPI1_CLK_ROOT; + break; + case 2: + clk = ECSPI2_CLK_ROOT; + break; + case 3: + clk = ECSPI3_CLK_ROOT; + break; + } + + clock_enable(clk, 0); + /* + * TODO: configure clock + */ + clock_enable(clk, 1); + + return 0; +} + #ifdef CONFIG_FEC_MXC int set_clk_enet(enum enet_freq type) { @@ -772,6 +797,19 @@ int clock_init(void) clock_enable(CCGR_TSENSOR, 1); clock_enable(CCGR_OCOTP, 1); + /* + * set ecspi roots + */ + clock_enable(CCGR_ECSPI1, 0); + clock_enable(CCGR_ECSPI2, 0); + clock_enable(CCGR_ECSPI3, 0); + clock_set_target_val(ECSPI1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); + clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); + clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); + clock_enable(CCGR_ECSPI1, 1); + clock_enable(CCGR_ECSPI2, 1); + clock_enable(CCGR_ECSPI3, 1); + /* config GIC ROOT to sys_pll2_200m */ clock_enable(CCGR_GIC, 0); clock_set_target_val(GIC_CLK_ROOT, -- 2.25.1