From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 01985C433EF for ; Wed, 12 Jan 2022 13:33:46 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 208CB83282; Wed, 12 Jan 2022 14:33:11 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="AyZaq6iu"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D225F831EF; Wed, 12 Jan 2022 14:33:08 +0100 (CET) Received: from EUR02-HE1-obe.outbound.protection.outlook.com (mail-he1eur02on061f.outbound.protection.outlook.com [IPv6:2a01:111:f400:fe05::61f]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id AC3058327C for ; Wed, 12 Jan 2022 14:32:57 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=gaurav.jain@nxp.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=kADir+/J8bmlF8ZDf1a/ZvhNqp/1/NgkGS0hQixSFiNrDmuBQ8Unw/BYU2Whnw8j53eEi8AQwLsFQx2ZxeutttgPPg2LOACc1hiINd1CqEd1eetTgA3qyDhIjl+lAm8AyM17CDHM4WMkCokB93pjLSnDG0RO3UrVTIDHvM47Ep6Z1k8++MkwHMbC2l/LCfHfMRunayg44X6DiSPzVdBfBxyovQmSC4mlQE5tF48cOgrG5bd+Xzb5edLA2B/wNGzyKwK012verPaD+bLj0ZDcJ2Cx3qoWFUNsdrCogdSrnWWgC0mayc5XqKsVef+ET4EffYYUuYP/z/Om/TmQShDjkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=iyiu789aUKBQrWbz2LevB1SI8BqitytH4pRd2dEl+qw=; b=mGZ6iwqLB0WyL81ZwZNIL3XFb31FJ+ID2bfsc+LWhmUANsBbTpc3/4uHmGpXQTJG2gXFrDlABJV0udm9XZOzhkWVg3xzTRa4eGOixC+oAHWUhXb+WgJL8z9u3I5zqGBe83LhGAfvWf/N4REuMOuOe1yqJ/n4mGdLaV9ANjKyroLQ/cYed4+KGW3mFku02UMDkEevbLhof28+jtimVzjdRFpceGd5UjOEAk1747VOzzcVPAgtPNe/dyMTBpqeyDQu3nlhlaczxqbRAz/aInUHL5w4KyzaR4BZhuxtXd24fL9GI0WfKVOmt9J32KMV+iZLau/fIzR299+eAM3exowFow== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=iyiu789aUKBQrWbz2LevB1SI8BqitytH4pRd2dEl+qw=; b=AyZaq6iuRk4QxFP++2NcETMU/t+M6CnDupxb0bOLhKRFAzQf7oE7O5ivquAWR9siufUSkVOHmqw0LsJ3XRzjJTbqrmIOf62M9CEh5q1UandFfb8gzhCnsrOsp3znAjR2ZTqxn5k1UpDMa+ksBiIB1QVKKkZ5Ingrl/WWp7gpJ/4= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from VI1PR04MB5342.eurprd04.prod.outlook.com (2603:10a6:803:46::16) by VI1PR04MB5853.eurprd04.prod.outlook.com (2603:10a6:803:e3::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4867.9; Wed, 12 Jan 2022 13:32:56 +0000 Received: from VI1PR04MB5342.eurprd04.prod.outlook.com ([fe80::ceb:f79:2700:ba2a]) by VI1PR04MB5342.eurprd04.prod.outlook.com ([fe80::ceb:f79:2700:ba2a%3]) with mapi id 15.20.4867.011; Wed, 12 Jan 2022 13:32:56 +0000 From: Gaurav Jain To: u-boot@lists.denx.de Cc: Stefano Babic , Fabio Estevam , Peng Fan , Simon Glass , Michael Walle , Priyanka Jain , Ye Li , Horia Geanta , Ji Luo , Franck Lenormand , Silvano Di Ninno , Sahil malhotra , Pankaj Gupta , Varun Sethi , "NXP i . MX U-Boot Team" , Shengzhou Liu , Mingkai Hu , Rajesh Bhagat , Meenakshi Aggarwal , Wasim Khan , Alison Wang , Pramod Kumar , Tang Yuantian , Adrian Alonso , Vladimir Oltean , Gaurav Jain Subject: [PATCH v10 09/14] crypto/fsl: i.MX8: Enable Job ring driver model. Date: Wed, 12 Jan 2022 19:01:22 +0530 Message-Id: <20220112133127.16880-10-gaurav.jain@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220112133127.16880-1-gaurav.jain@nxp.com> References: <20220112133127.16880-1-gaurav.jain@nxp.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SI2PR02CA0035.apcprd02.prod.outlook.com (2603:1096:4:195::22) To VI1PR04MB5342.eurprd04.prod.outlook.com (2603:10a6:803:46::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 54aa37f4-70cb-4394-086a-08d9d5d00ac8 X-MS-TrafficTypeDiagnostic: VI1PR04MB5853:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:16; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4N0dH+RG3oUqRFsjY0+/3tRsP9iJ2QAoOLU0VziKQXM18LZ9q97On6BLlMt4ikV/T43jHA/PA8Nwln1opB99gGPY+NwzEnwmK8kP605j/RiKMPNMDU7yGZ/tEKPibudfo4FcWDMEvlWVAyfR8+qMdX0G2Lufco/4Acta+elabh4Z42TwUaOoxnVauSFGmPgq0grl6KSDa5cmJkgWszdAYRc7GW7PXVipgZmd71fhvQe0/61/7rkPJjHaR5m1XH4Ya3FTvT6jYVr/ByIFenS4Rhf7nJY0ePtQ3ahiN49GyGZbB7KMA7h9qe0faJ5B4kPFuXTXViEl198sTC73PnqP5lxZNwYQT/tu8oNHmKxKnVFZ9V+Yd+sQduYdXnl05FEOYuUjN6L1DF0fKrJkerWBBFBDsOKvnOKP1q1Lke++Tvi7FRqkdi32qHH3Ioy8VTfeLXvj5izapX7E5q0EzGQT1i9KOs4Y+Bruyn/Epj9efECEnR3OpIRWZpbp7sFbND4tyu8eAvW0KTuOnkfavufvOpIxqkMRckyECZub9AgKTla/MrV7WK7jwg1GOWolfHOLFD9oF9KFyxIx/ElloV6FXB4aVj84aV5UI9NfxxgLefj0TLPqV9NZjZnfyFxZHcUnE3usdazY6yWB//lR1dxAtOkiftH8fW2qpuyGt0sbVpmWoQt86WS8Q3AzcHq2WRLlXa02fK4bqSnJAXT9+fGGgw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:VI1PR04MB5342.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(44832011)(6486002)(38100700002)(6666004)(186003)(38350700002)(6512007)(316002)(26005)(2616005)(86362001)(508600001)(36756003)(6916009)(55236004)(66946007)(6506007)(66556008)(52116002)(4326008)(66476007)(8676002)(8936002)(5660300002)(83380400001)(2906002)(1076003)(54906003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?Um9mcDMwOUpTdW80WllBRFZQOGJTRUk4NHNZWjMydVdONlRsTC94dXdjcWZL?= =?utf-8?B?Sm40NWNWSlVvOHk5bEI5STJIdko1a0pqMmlTdVlUbFk4SjhLTFpHUVpzZXha?= =?utf-8?B?QzVMSDNpakVMZndsR1krbmhMYytpNytJWHVSMGx5WFhJSmgvVS9ZUEZWMW4v?= =?utf-8?B?M0UzbUVTQTBMWmh4Qk8yNHI2TWN1QnNpaGVLWVZwaXR1WGhBbUtpZFpWRUVr?= =?utf-8?B?R1VQTzdJVzVMMkQvVXBabkVKTk1admtORXlSNXJacURmWWRFcGlRcjRWSFpy?= =?utf-8?B?VkFiTkxEMGhhcmtwMjdPQU1CK1VCQXBTQnRDYWdMUWxLUmRKd2RERTV5aE9r?= =?utf-8?B?clV4MFN0blhNdWVVQkJRcitvS1FBeUNkVVFqQ2RuOXJoQ2tmL2d4UUR6N0wv?= =?utf-8?B?bFdsNEV0Tm5XNGh1ZkhQT28vSS9KaE0wa1Ywa3J4ZDl2VjVLMGFLYXgvSU9h?= =?utf-8?B?RmdITjVqL0NIcHVzbjRjTko5UUF4bFJRa1FJelIzeWtKRndoVE10ZWRxNk9s?= =?utf-8?B?T3BwU0tZM2NJOERCdmIxRGovczY5Z1U3bWlBbHVqSlJkdFJrMmhxZnVSNndQ?= =?utf-8?B?QVZvRGh5UFBaVG0yT1dQdnlScFZsRHJvdGNyUmx0ZUxvemlXMnNXZ0J0d1ls?= =?utf-8?B?cUVTNTVUdjAxMmNOLzhTSElyRjJVRW43dXBaZFJxQUxSVkdwbTZNU3JETTM0?= =?utf-8?B?Z0V1R24wb3hFTG1vTE5xUDU1Ly9SWEtwMW8zajZCYkhkclp0UUZKVFduQmFU?= =?utf-8?B?VmYzMkxNbk5VUjh6cjdWRUQ2bXB4Zkpic3hVMkFHUnhjOUV5U1hSZkJVRjhS?= =?utf-8?B?eUxNZ21TNXdGVC9DZXlHZEQ5YXdiRFlzZDRyTjUydWl3MTk1a1FDT2dvcTB6?= =?utf-8?B?Mm9EVVJZcGR1KzF0aXB4Rk01S0JsMi9zWG5zUDR3VFAvSUQyeEc2R244VTho?= =?utf-8?B?UEpvVUh5VG1IVVFjWU40RDRMU250YTUxNlNPY0NWSDQ4UGlYL1BBNDNsd3lL?= =?utf-8?B?a1FjdEQyYXJ6bFArN0tSbnRoVEpOWGJ0Z0xzVFppcFhPcWw1YjFsWnFoRHFs?= =?utf-8?B?KzFwaCszU3dua0l6RzRJc3JZU1YzNllrSlBocWlPL1l6REFOcG5mdDQvdnZr?= =?utf-8?B?R0hkL3FRK0xNMlhpSG9ndC90NVdGOTl2WWc1b0JWVndPNTNEblFTRytkR3JT?= =?utf-8?B?cW1ObXZqTmFRWGZoZnJBSE5WdFQ3RFp4REk3akFLVjNXbTJpSklENFpZbzFP?= =?utf-8?B?MFpBWVYyY29pVUxhUlVVRkYxcEhZN3hjM1JzZDhEdXQ4SzhLSDVpR3huNFht?= =?utf-8?B?NFNtVk95VUx4aitrRXFLZVVjd1lZbVF6MVB1WGsrQTJDU1JYeDhGV1k3cHB5?= =?utf-8?B?ZkxDUmZybVBmdWZUajJiMmpKTGYwTzNwUzJtOFN5bTFrUjFvcjlwU0JobU92?= =?utf-8?B?NTg4YlJuRC9CcTV6VHhCamZKU2J3cGZsRXcvY1FxZXd1cUN5VWM2T2lWZGV5?= =?utf-8?B?M051Z0h0aFJldGF3UTczaW9QOGZOQVg0N1k4c0prWXA3emxKQWsxWUd3SEVG?= =?utf-8?B?S0t5UUI3ZnF4ZDRzR3hJRisxMEJYWXh3ZzVKcWFuTElJaUVyblE2VEdmK1p5?= =?utf-8?B?d2xFWjhUdTBXd0VDZEV3aVJTeitaMTN5UnNPSG9PSzQ2YkVGL0FqR1poSTZI?= =?utf-8?B?ZzJHeUtMYUdMVzBrWFk2MUZrTUhvOFJocW9lckttRDlZNEZYTy9JdmE5WnZ4?= =?utf-8?B?WGVpTm5pOUExWldBWXdDdEFSUEFDREw2ZVo1eEZSNjEvamxmY0xIeTBGQXFE?= =?utf-8?B?QmNvTitvNStMZ2ZhalBkUThrZ0RWa3JuLzhnRkxUdnJubUw1dXZyRzZHSUZr?= =?utf-8?B?VE5HdXVpWnVlUmpRWkkrcWRKZTd6UDRkNEpTb3g1V3dyR3pLeWxvNjhLNWdr?= =?utf-8?B?azVLSmlCc21PbDdscjNMM3Vpc0l2aUlQdnJEL1BlV3BEV3dLR1kvcXJVRXl4?= =?utf-8?B?bTFvNjJ0Mi85ci80Q0NyVWhVY0taWkowQkQ4alNlRTlSazVNNkpkOXRhVVEr?= =?utf-8?B?eUZTang5UEpWM1ZYdEdLUzlrL1hoRG9CY1hjdzBJYy9ocHdiaDl5QUFNQldh?= =?utf-8?B?NUtKdmJnd0o4TjFUaHlvWGVMcDN3dkpBbXlORTFwYm0rMnZxMzdxbTlqQ3RX?= =?utf-8?Q?kEZkcXh+SCF1LB5nt5Dlxos=3D?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 54aa37f4-70cb-4394-086a-08d9d5d00ac8 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5342.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2022 13:32:56.3241 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2ZINTf14Bdlk++uv27qoALih8hOOfrx/mxe2VlCNwwdC93w88yDh2oE8bFiprAyxA9Ikvn+kJRkqV6Jdz9HXNA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB5853 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean i.MX8(QM/QXP) - added support for JR driver model. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain Signed-off-by: Horia Geantă Reviewed-by: Ye Li --- arch/arm/Kconfig | 3 ++ arch/arm/include/asm/arch-imx8/imx-regs.h | 5 ++- arch/arm/mach-imx/cmd_dek.c | 1 + arch/arm/mach-imx/imx8/Kconfig | 7 ++++ arch/arm/mach-imx/imx8/cpu.c | 18 ++++++++- board/freescale/imx8qm_mek/spl.c | 6 ++- board/freescale/imx8qxp_mek/spl.c | 6 ++- drivers/crypto/fsl/Kconfig | 2 +- drivers/crypto/fsl/jr.c | 47 ++++++++++++++++++++++- include/fsl_sec.h | 12 +++--- 10 files changed, 91 insertions(+), 16 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5e3c2ed3eb..dd01856b3e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -809,6 +809,9 @@ config ARCH_LPC32XX config ARCH_IMX8 bool "NXP i.MX8 platform" select ARM64 + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SEC_LE select DM select GPIO_EXTRA_HEADER select MACH_IMX diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h index ed6e05e556..2d64b0604b 100644 --- a/arch/arm/include/asm/arch-imx8/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8/imx-regs.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP */ #ifndef __ASM_ARCH_IMX8_REGS_H__ @@ -47,4 +47,7 @@ #define USB_BASE_ADDR 0x5b0d0000 #define USB_PHY0_BASE_ADDR 0x5b100000 +#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000) +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + #endif /* __ASM_ARCH_IMX8_REGS_H__ */ diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index 89da89c51d..04c4b20a84 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index b43739e5c6..f969833bab 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -8,6 +8,7 @@ config AHAB_BOOT config IMX8 bool + select HAS_CAAM config MU_BASE_SPL hex "MU base address used in SPL" @@ -72,6 +73,9 @@ config TARGET_IMX8QM_MEK bool "Support i.MX8QM MEK board" select BOARD_LATE_INIT select IMX8QM + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_CONGA_QMX8 bool "Support congatec conga-QMX8 board" @@ -89,6 +93,9 @@ config TARGET_IMX8QXP_MEK bool "Support i.MX8QXP MEK board" select BOARD_LATE_INIT select IMX8QXP + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL endchoice diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index ee5cc47903..991908fbd3 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP */ #include @@ -89,6 +89,22 @@ int arch_cpu_init_dm(void) return 0; } +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize %s: %d\n", dev->name, ret); + } + + return 0; +} +#endif + int print_bootinfo(void) { enum boot_device bt_dev = get_boot_device(); diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c index 944ba745c0..332a662dee 100644 --- a/board/freescale/imx8qm_mek/spl.c +++ b/board/freescale/imx8qm_mek/spl.c @@ -1,7 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP * - * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -24,6 +24,8 @@ void spl_board_init(void) { struct udevice *dev; + uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev); + uclass_find_first_device(UCLASS_MISC, &dev); for (; dev; uclass_find_next_device(&dev)) { diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c index ae6b64ff6e..2fa6840056 100644 --- a/board/freescale/imx8qxp_mek/spl.c +++ b/board/freescale/imx8qxp_mek/spl.c @@ -1,7 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP * - * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -39,6 +39,8 @@ void spl_board_init(void) { struct udevice *dev; + uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev); + uclass_find_first_device(UCLASS_MISC, &dev); for (; dev; uclass_find_next_device(&dev)) { diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index 231eb00b5f..e03fcdd9c7 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -12,7 +12,7 @@ config FSL_CAAM config CAAM_64BIT bool - default y if PHYS_64BIT && !ARCH_IMX8M + default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8 help Select Crypto driver for 64 bits CAAM version diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 4e7accfb89..a84440ab10 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "jr.h" #include "jobdesc.h" #include "desc_constr.h" @@ -121,7 +122,9 @@ static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam) static int jr_init(uint8_t sec_idx, struct caam_regs *caam) { struct jobring *jr = &caam->jr[sec_idx]; - +#if CONFIG_IS_ENABLED(OF_CONTROL) + ofnode scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu"); +#endif memset(jr, 0, sizeof(struct jobring)); jr->jq_id = caam->jrid; @@ -146,7 +149,11 @@ static int jr_init(uint8_t sec_idx, struct caam_regs *caam) memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t)); memset(jr->output_ring, 0, jr->op_size); +#if CONFIG_IS_ENABLED(OF_CONTROL) + if (!ofnode_valid(scu_node)) +#endif start_jr(caam); + jr_initregs(sec_idx, caam); return 0; @@ -681,6 +688,13 @@ int sec_init_idx(uint8_t sec_idx) caam_st.jrid = JR_ID; caam = &caam_st; #endif +#if CONFIG_IS_ENABLED(OF_CONTROL) + ofnode scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu"); + + if (ofnode_valid(scu_node)) + goto init; +#endif + ccsr_sec_t *sec = caam->sec; uint32_t mcr = sec_in32(&sec->mcfgr); #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M) @@ -742,12 +756,19 @@ int sec_init_idx(uint8_t sec_idx) liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT; liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT; #endif +#endif +#if CONFIG_IS_ENABLED(OF_CONTROL) +init: #endif ret = jr_init(sec_idx, caam); if (ret < 0) { printf("SEC%u: initialization failed\n", sec_idx); return -1; } +#if CONFIG_IS_ENABLED(OF_CONTROL) + if (ofnode_valid(scu_node)) + return ret; +#endif #ifdef CONFIG_FSL_CORENET ret = sec_config_pamu_table(liodn_ns, liodn_s); @@ -781,6 +802,23 @@ int sec_init(void) } #if CONFIG_IS_ENABLED(DM) +static int jr_power_on(ofnode node) +{ +#if CONFIG_IS_ENABLED(POWER_DOMAIN) + struct udevice __maybe_unused jr_dev; + struct power_domain pd; + + dev_set_ofnode(&jr_dev, node); + + /* Power on Job Ring before access it */ + if (!power_domain_get(&jr_dev, &pd)) { + if (power_domain_on(&pd)) + return -EINVAL; + } +#endif + return 0; +} + static int caam_jr_ioctl(struct udevice *dev, unsigned long request, void *buf) { if (request != CAAM_JR_RUN_DESC) @@ -793,7 +831,7 @@ static int caam_jr_probe(struct udevice *dev) { struct caam_regs *caam = dev_get_priv(dev); fdt_addr_t addr; - ofnode node; + ofnode node, scu_node; unsigned int jr_node = 0; caam_dev = dev; @@ -818,6 +856,11 @@ static int caam_jr_probe(struct udevice *dev) jr_node = jr_node >> 4; caam->jrid = jr_node - 1; + scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu"); + if (ofnode_valid(scu_node)) { + if (jr_power_on(node)) + return -EINVAL; + } break; } } diff --git a/include/fsl_sec.h b/include/fsl_sec.h index c4121696f8..7b6e3e2c20 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -3,7 +3,7 @@ * Common internal memory map for some Freescale SoCs * * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP */ #ifndef __FSL_SEC_H @@ -194,12 +194,10 @@ typedef struct ccsr_sec { #define SEC_CHAVID_LS_RNG_SHIFT 16 #define SEC_CHAVID_RNG_LS_MASK 0x000f0000 -#define CONFIG_JRSTARTR_JR0 0x00000001 - struct jr_regs { #if defined(CONFIG_SYS_FSL_SEC_LE) && \ !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ - defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)) u32 irba_l; u32 irba_h; #else @@ -214,7 +212,7 @@ struct jr_regs { u32 irja; #if defined(CONFIG_SYS_FSL_SEC_LE) && \ !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ - defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)) u32 orba_l; u32 orba_h; #else @@ -248,7 +246,7 @@ struct jr_regs { struct sg_entry { #if defined(CONFIG_SYS_FSL_SEC_LE) && \ !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ - defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)) uint32_t addr_lo; /* Memory Address - lo */ uint32_t addr_hi; /* Memory Address of start of buffer - hi */ #else @@ -268,7 +266,7 @@ struct sg_entry { }; #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ - defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) /* Job Ring Base Address */ #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1)) /* Secure Memory Offset varies accross versions */ -- 2.17.1