From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 262FBC433EF for ; Tue, 24 May 2022 16:18:06 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 30A40842D2; Tue, 24 May 2022 18:17:24 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id CADD383ABF; Tue, 24 May 2022 18:16:57 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 858DE842A6 for ; Tue, 24 May 2022 18:16:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B817323A; Tue, 24 May 2022 09:16:52 -0700 (PDT) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 63BE63F66F; Tue, 24 May 2022 09:16:51 -0700 (PDT) Date: Tue, 24 May 2022 17:10:26 +0100 From: Andre Przywara To: Jagan Teki Cc: Jesse Taube , Icenowy Zheng , Yifan Gu , Giulio Benetti , George Hilliard , Samuel Holland , Jernej Skrabec , linux-sunxi@lists.linux.dev, u-boot@lists.denx.de Subject: Re: [PATCH 1/7] clk: sunxi: implement clock driver for suniv f1c100s Message-ID: <20220524171026.313bfbed@donnerap.cambridge.arm.com> In-Reply-To: <20220503212040.27884-2-andre.przywara@arm.com> References: <20220503212040.27884-1-andre.przywara@arm.com> <20220503212040.27884-2-andre.przywara@arm.com> Organization: ARM X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Tue, 3 May 2022 22:20:34 +0100 Andre Przywara wrote: > From: George Hilliard > > The f1c100s has a clock tree similar to those of other sunxi parts. > Add support for it. > > Signed-off-by: George Hilliard > Signed-off-by: Yifan Gu > Acked-by: Sean Anderson > [Andre: add PIO and I2C] > Signed-off-by: Andre Przywara Applied to sunxi/master. Thanks, Andre > --- > drivers/clk/sunxi/Kconfig | 7 ++++ > drivers/clk/sunxi/Makefile | 1 + > drivers/clk/sunxi/clk_f1c100s.c | 74 +++++++++++++++++++++++++++++++++ > 3 files changed, 82 insertions(+) > create mode 100644 drivers/clk/sunxi/clk_f1c100s.c > > diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig > index f19908113e1..bf11fad6eef 100644 > --- a/drivers/clk/sunxi/Kconfig > +++ b/drivers/clk/sunxi/Kconfig > @@ -10,6 +10,13 @@ config CLK_SUNXI > > if CLK_SUNXI > > +config CLK_SUNIV_F1C100S > + bool "Clock driver for Allwinner F1C100s" > + default MACH_SUNIV > + help > + This enables common clock driver support for platforms based > + on Allwinner F1C100s SoC. > + > config CLK_SUN4I_A10 > bool "Clock driver for Allwinner A10/A20" > default MACH_SUN4I || MACH_SUN7I > diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile > index 48a48a2f000..895da02ebea 100644 > --- a/drivers/clk/sunxi/Makefile > +++ b/drivers/clk/sunxi/Makefile > @@ -8,6 +8,7 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o > > obj-$(CONFIG_CLK_SUNXI) += clk_sun6i_rtc.o > > +obj-$(CONFIG_CLK_SUNIV_F1C100S) += clk_f1c100s.o > obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o > obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o > obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o > diff --git a/drivers/clk/sunxi/clk_f1c100s.c b/drivers/clk/sunxi/clk_f1c100s.c > new file mode 100644 > index 00000000000..72cf8a6e5c0 > --- /dev/null > +++ b/drivers/clk/sunxi/clk_f1c100s.c > @@ -0,0 +1,74 @@ > +// SPDX-License-Identifier: (GPL-2.0+) > +/* > + * Copyright (C) 2019 George Hilliard . > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +static struct ccu_clk_gate f1c100s_gates[] = { > + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), > + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), > + [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), > + [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), > + [CLK_BUS_OTG] = GATE(0x060, BIT(24)), > + > + [CLK_BUS_I2C0] = GATE(0x068, BIT(16)), > + [CLK_BUS_I2C1] = GATE(0x068, BIT(17)), > + [CLK_BUS_I2C2] = GATE(0x068, BIT(18)), > + [CLK_BUS_PIO] = GATE(0x068, BIT(19)), > + > + [CLK_BUS_UART0] = GATE(0x06c, BIT(20)), > + [CLK_BUS_UART1] = GATE(0x06c, BIT(21)), > + [CLK_BUS_UART2] = GATE(0x06c, BIT(22)), > + > + [CLK_USB_PHY0] = GATE(0x0cc, BIT(1)), > +}; > + > +static struct ccu_reset f1c100s_resets[] = { > + [RST_USB_PHY0] = RESET(0x0cc, BIT(0)), > + > + [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), > + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), > + [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), > + [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)), > + [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), > + > + [RST_BUS_I2C0] = RESET(0x2d0, BIT(16)), > + [RST_BUS_I2C1] = RESET(0x2d0, BIT(17)), > + [RST_BUS_I2C2] = RESET(0x2d0, BIT(18)), > + [RST_BUS_UART0] = RESET(0x2d0, BIT(20)), > + [RST_BUS_UART1] = RESET(0x2d0, BIT(21)), > + [RST_BUS_UART2] = RESET(0x2d0, BIT(22)), > +}; > + > +static const struct ccu_desc f1c100s_ccu_desc = { > + .gates = f1c100s_gates, > + .resets = f1c100s_resets, > +}; > + > +static int f1c100s_clk_bind(struct udevice *dev) > +{ > + return sunxi_reset_bind(dev, ARRAY_SIZE(f1c100s_resets)); > +} > + > +static const struct udevice_id f1c100s_clk_ids[] = { > + { .compatible = "allwinner,suniv-f1c100s-ccu", > + .data = (ulong)&f1c100s_ccu_desc }, > + { } > +}; > + > +U_BOOT_DRIVER(clk_suniv_f1c100s) = { > + .name = "suniv_f1c100s_ccu", > + .id = UCLASS_CLK, > + .of_match = f1c100s_clk_ids, > + .priv_auto = sizeof(struct ccu_priv), > + .ops = &sunxi_clk_ops, > + .probe = sunxi_clk_probe, > + .bind = f1c100s_clk_bind, > +};