From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 01B89C43334 for ; Fri, 15 Jul 2022 16:28:13 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 41EFB8110C; Fri, 15 Jul 2022 18:28:11 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tinet.cat Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id E957681118; Fri, 15 Jul 2022 18:28:09 +0200 (CEST) Received: from mx1.tinet.cat (mx1.tinet.cat [195.77.216.146]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3E1D580755 for ; Fri, 15 Jul 2022 18:28:07 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tinet.cat Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=xdrudis@tinet.cat X-ASG-Debug-ID: 1657902484-163e7b70c86bff20001-4l7tJC Received: from smtp01.tinet.cat (smtp01.tinet.org [195.77.216.131]) by mx1.tinet.cat with ESMTP id ZPHUwi5TSfEHFVug; Fri, 15 Jul 2022 18:28:04 +0200 (CEST) X-Barracuda-Envelope-From: xdrudis@tinet.cat X-Barracuda-Effective-Source-IP: smtp01.tinet.org[195.77.216.131] X-Barracuda-Apparent-Source-IP: 195.77.216.131 Received: from begut (99.red-79-152-185.dynamicip.rima-tde.net [79.152.185.99]) by smtp01.tinet.cat (Postfix) with ESMTPSA id 6494A605E0C3; Fri, 15 Jul 2022 18:28:04 +0200 (CEST) Date: Fri, 15 Jul 2022 18:28:02 +0200 From: Xavier Drudis Ferran To: u-boot@lists.denx.de Cc: Simon Glass , Philipp Tomsich , Kever Yang Subject: [PATCH v2 2/5] Add XTX SPI NOR 4MiB Flash chip in Rock Pi 4 boards from rev 1.4 on. Message-ID: <20220715162802.GC2143@begut> X-ASG-Orig-Subj: [PATCH v2 2/5] Add XTX SPI NOR 4MiB Flash chip in Rock Pi 4 boards from rev 1.4 on. MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline User-Agent: Mutt/1.10.1 (2018-07-13) X-Barracuda-Connect: smtp01.tinet.org[195.77.216.131] X-Barracuda-Start-Time: 1657902484 X-Barracuda-URL: https://webmail.tinet.cat:443/cgi-mod/mark.cgi X-Barracuda-Scan-Msg-Size: 3498 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.8852 1.0000 3.0690 X-Barracuda-Spam-Score: 3.07 X-Barracuda-Spam-Status: No, SCORE=3.07 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=6.0 KILL_LEVEL=8.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.99399 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Configure Rock Pi 4 to boot from SPI NOR Flash. Based on flash chip, board documentation and tests, this is the fastest I could use it. This seems to be the minimum necessary configuration for Rock Pi 4 to be able to boot from SPI NOR Flash. With the next patch, it works to sf probe 1:0, sf read, sf erase, sf write, sf read and then boot linux and flashrom can write to it. Sometimes flashrom seems to fail to write when at U-Boot stage there was no sf read or write, not sure why. Changes from v1: - include CONFIG_SF_DEFAULT_BUS=1 now that numeration will be unified between U-Boot and SPL (at patch 5/5) Signed-off-by: Xavier Drudis Ferran Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang --- arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 18 ++++++++++++++++++ configs/rock-pi-4-rk3399_defconfig | 22 ++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi index c17e769f64..4c2fe8f6bc 100644 --- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi @@ -15,3 +15,21 @@ &vdd_log { regulator-init-microvolt = <950000>; }; + +&spi1 { + status = "okay"; + spi-max-frequency = <40000000>; + spi-activate-delay = <12000>; /* 12 ms */ + + norflash: flash@0 { + compatible = "rockchip,spidev", "jedec,spi-nor"; + reg = <0>; + + spi-max-frequency = <40000000>; + spi-cpha; + spi-cpol; + + status = "okay"; + u-boot,dm-pre-reloc; + }; +}; diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index eb5778dc17..93a8d3fd23 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -13,6 +13,8 @@ CONFIG_BOOTSTAGE_STASH_ADDR=0x3fbd0000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_ENV_OFFSET_REDUND=0x3e0000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y @@ -36,6 +38,11 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI_FLASH_MTD=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xb0000 CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y @@ -57,21 +64,36 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_MODE=0x3 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_MTD=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y CONFIG_PCI=y +CONFIG_SPL_PHY=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -- 2.20.1