From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DDBE8C43334 for ; Mon, 18 Jul 2022 16:20:17 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4A61583FC5; Mon, 18 Jul 2022 18:20:15 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 480B283FCE; Mon, 18 Jul 2022 18:20:14 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 7EDC483F97 for ; Mon, 18 Jul 2022 18:20:11 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4A04A1042; Mon, 18 Jul 2022 09:20:11 -0700 (PDT) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8EFBD3F73D; Mon, 18 Jul 2022 09:20:09 -0700 (PDT) Date: Mon, 18 Jul 2022 17:20:06 +0100 From: Andre Przywara To: Samuel Holland Cc: u-boot@lists.denx.de, Jagan Teki , Dario Binacchi , Hans de Goede , Lukasz Majewski , Michael Trimarchi , Sean Anderson , Simon Glass Subject: Re: [PATCH 2/6] pinctrl: sunxi: Add NAND pinmuxes Message-ID: <20220718172006.28729c32@donnerap.cambridge.arm.com> In-Reply-To: <20220714031526.33697-3-samuel@sholland.org> References: <20220714031526.33697-1-samuel@sholland.org> <20220714031526.33697-3-samuel@sholland.org> Organization: ARM X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Wed, 13 Jul 2022 22:15:22 -0500 Samuel Holland wrote: Hi, > NAND is always at function 2 on port C. Indeed. > > Pin lists and mux values were taken from the Linux drivers. Compared against the manuals. I didn't bother the check the pin ranges (I think some additional CS pins were not covered by the comments), but that shouldn't matter anyways. Reviewed-by: Andre Przywara > Signed-off-by: Samuel Holland Cheers, Andre P.S.: I see that the A83T kernel pinctrl driver uses "nand" for *some* pins instead of "nand0", not sure if that should to be fixed, or if it's too late for that (not that NAND is mentioned at all in the A83T DT files ...) > --- > > drivers/pinctrl/sunxi/pinctrl-sunxi.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c > index 9ce2bc1b3afb..b10e3e7b0690 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c > +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c > @@ -268,6 +268,7 @@ static const struct sunxi_pinctrl_function sun4i_a10_pinctrl_functions[] = { > #endif > { "mmc2", 3 }, /* PC6-PC15 */ > { "mmc3", 2 }, /* PI4-PI9 */ > + { "nand0", 2 }, /* PC0-PC24 */ > { "spi0", 3 }, /* PC0-PC2, PC23 */ > #if IS_ENABLED(CONFIG_UART0_PORT_F) > { "uart0", 4 }, /* PF2-PF4 */ > @@ -292,6 +293,7 @@ static const struct sunxi_pinctrl_function sun5i_a13_pinctrl_functions[] = { > { "mmc0", 2 }, /* PF0-PF5 */ > { "mmc1", 2 }, /* PG3-PG8 */ > { "mmc2", 3 }, /* PC6-PC15 */ > + { "nand0", 2 }, /* PC0-PC19 */ > { "spi0", 3 }, /* PC0-PC3 */ > #if IS_ENABLED(CONFIG_UART0_PORT_F) > { "uart0", 4 }, /* PF2-PF4 */ > @@ -318,6 +320,7 @@ static const struct sunxi_pinctrl_function sun6i_a31_pinctrl_functions[] = { > { "mmc1", 2 }, /* PG0-PG5 */ > { "mmc2", 3 }, /* PC6-PC15, PC24 */ > { "mmc3", 4 }, /* PC6-PC15, PC24 */ > + { "nand0", 2 }, /* PC0-PC26 */ > { "spi0", 3 }, /* PC0-PC2, PC27 */ > #if IS_ENABLED(CONFIG_UART0_PORT_F) > { "uart0", 3 }, /* PF2-PF4 */ > @@ -361,6 +364,7 @@ static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = { > { "mmc1", 4 }, /* PG0-PG5 */ > #endif > { "mmc2", 3 }, /* PC5-PC15, PC24 */ > + { "nand0", 2 }, /* PC0-PC24 */ > { "spi0", 3 }, /* PC0-PC2, PC23 */ > #if IS_ENABLED(CONFIG_UART0_PORT_F) > { "uart0", 4 }, /* PF2-PF4 */ > @@ -384,6 +388,7 @@ static const struct sunxi_pinctrl_function sun8i_a23_pinctrl_functions[] = { > { "mmc0", 2 }, /* PF0-PF5 */ > { "mmc1", 2 }, /* PG0-PG5 */ > { "mmc2", 3 }, /* PC5-PC16 */ > + { "nand0", 2 }, /* PC0-PC16 */ > { "spi0", 3 }, /* PC0-PC3 */ > #if IS_ENABLED(CONFIG_UART0_PORT_F) > { "uart0", 3 }, /* PF2-PF4 */ > @@ -421,6 +426,7 @@ static const struct sunxi_pinctrl_function sun8i_a33_pinctrl_functions[] = { > { "mmc0", 2 }, /* PF0-PF5 */ > { "mmc1", 2 }, /* PG0-PG5 */ > { "mmc2", 3 }, /* PC5-PC16 */ > + { "nand0", 2 }, /* PC0-PC16 */ > { "spi0", 3 }, /* PC0-PC3 */ > #if IS_ENABLED(CONFIG_UART0_PORT_F) > { "uart0", 3 }, /* PF2-PF4 */ > @@ -447,6 +453,7 @@ static const struct sunxi_pinctrl_function sun8i_a83t_pinctrl_functions[] = { > { "mmc0", 2 }, /* PF0-PF5 */ > { "mmc1", 2 }, /* PG0-PG5 */ > { "mmc2", 3 }, /* PC5-PC16 */ > + { "nand0", 2 }, /* PC0-PC18 */ > { "spi0", 3 }, /* PC0-PC3 */ > #if IS_ENABLED(CONFIG_UART0_PORT_F) > { "uart0", 3 }, /* PF2-PF4 */ > @@ -487,6 +494,7 @@ static const struct sunxi_pinctrl_function sun8i_h3_pinctrl_functions[] = { > { "mmc0", 2 }, /* PF0-PF5 */ > { "mmc1", 2 }, /* PG0-PG5 */ > { "mmc2", 3 }, /* PC5-PC16 */ > + { "nand0", 2 }, /* PC0-PC16 */ > { "spi0", 3 }, /* PC0-PC3 */ > #if IS_ENABLED(CONFIG_UART0_PORT_F) > { "uart0", 3 }, /* PF2-PF4 */ > @@ -553,6 +561,7 @@ static const struct sunxi_pinctrl_function sun9i_a80_pinctrl_functions[] = { > { "mmc0", 2 }, /* PF0-PF5 */ > { "mmc1", 2 }, /* PG0-PG5 */ > { "mmc2", 3 }, /* PC6-PC16 */ > + { "nand0", 2 }, /* PC0-PC18 */ > { "spi0", 3 }, /* PC0-PC2, PC19 */ > #if IS_ENABLED(CONFIG_UART0_PORT_F) > { "uart0", 4 }, /* PF2-PF4 */ > @@ -592,6 +601,7 @@ static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = { > { "mmc0", 2 }, /* PF0-PF5 */ > { "mmc1", 2 }, /* PG0-PG5 */ > { "mmc2", 3 }, /* PC1-PC16 */ > + { "nand0", 2 }, /* PC0-PC16 */ > { "pwm", 2 }, /* PD22 */ > { "spi0", 4 }, /* PC0-PC3 */ > #if IS_ENABLED(CONFIG_UART0_PORT_F) > @@ -633,6 +643,7 @@ static const struct sunxi_pinctrl_function sun50i_h5_pinctrl_functions[] = { > { "mmc0", 2 }, /* PF0-PF5 */ > { "mmc1", 2 }, /* PG0-PG5 */ > { "mmc2", 3 }, /* PC1-PC16 */ > + { "nand0", 2 }, /* PC0-PC16 */ > { "spi0", 3 }, /* PC0-PC3 */ > #if IS_ENABLED(CONFIG_UART0_PORT_F) > { "uart0", 3 }, /* PF2-PF4 */ > @@ -659,6 +670,7 @@ static const struct sunxi_pinctrl_function sun50i_h6_pinctrl_functions[] = { > { "mmc0", 2 }, /* PF0-PF5 */ > { "mmc1", 2 }, /* PG0-PG5 */ > { "mmc2", 3 }, /* PC1-PC14 */ > + { "nand0", 2 }, /* PC0-PC16 */ > { "spi0", 4 }, /* PC0-PC7 */ > #if IS_ENABLED(CONFIG_UART0_PORT_F) > { "uart0", 3 }, /* PF2-PF4 */ > @@ -696,6 +708,7 @@ static const struct sunxi_pinctrl_function sun50i_h616_pinctrl_functions[] = { > { "mmc0", 2 }, /* PF0-PF5 */ > { "mmc1", 2 }, /* PG0-PG5 */ > { "mmc2", 3 }, /* PC0-PC16 */ > + { "nand0", 2 }, /* PC0-PC16 */ > { "spi0", 4 }, /* PC0-PC7, PC15-PC16 */ > #if IS_ENABLED(CONFIG_UART0_PORT_F) > { "uart0", 3 }, /* PF2-PF4 */