From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5790FC19F2A for ; Thu, 4 Aug 2022 14:30:00 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 08D0484869; Thu, 4 Aug 2022 16:29:07 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="LX2HAP2C"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id C054D84869; Thu, 4 Aug 2022 16:29:04 +0200 (CEST) Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8428C8486B for ; Thu, 4 Aug 2022 16:29:00 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-pj1-x102f.google.com with SMTP id b4so9525509pji.4 for ; Thu, 04 Aug 2022 07:29:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KK7kE+Fwoy4t0bE4cd6Xsho7n164CKoBSu6EWO9auq8=; b=LX2HAP2CSrsgZ8TqrQuSvDLBPViLE9R6VNPx1RFwKpg4bzcMj0XD27S5nHWkfBsP1C HQo4uKb7NZONsIJdAG1aVFC+lzLMVzfwWJmMZ82Wzpd4Jpn4Lu3tFy3/dYB2bsTKrg/7 Sk63usi4GgID3CQ/n5ZnN3C5ewU18J8KxupHRKMyNk3fWQLC4SuDegNE2Nc+NvJS5qiJ mAUGUm4P5+89yi+0lREy1MMYj/rZAR/hvkKqtOnHfN2LE0uaEbbZ5Zv9onIY9PWoMI76 7v/0QCRAN1t1f30pVmW6N7FftXEu6d0AQ/tIReoQIbAKSpSIkVgOEf13xYAU7S+dTJh4 zJow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KK7kE+Fwoy4t0bE4cd6Xsho7n164CKoBSu6EWO9auq8=; b=lEYZPmmOmHMhlLA4MR2CxzUUQNKTxsXPdRROovWnlm6JlcZwYiWpEKmQPbb4IJfFrn fYlTvReB3WoMrhDjSm0rQlUgGwyv2yApxBJ7Kr8qBmOPtvFFj59gG/qTHdcsiqonhJZ/ oQ0bURFgCzcQY+BgCfDLG2lsiSaOspGyINi/OMPDgZAglm3fazml7MHGOhJ6SjruOfoc C7y1NeWLwUFs1qGO7tVY4HjYUX6i4GKe1X/X1K3Lwmroop3w9rPYEO0+GytDfsdpKR6/ iWG+mTOLQyFuDVn2bVayZe8OxP/JRpQ4msrwpqJYXdSfeaWLD5fTgbu9d07UEWuRre8g HILg== X-Gm-Message-State: ACgBeo3JeBk9L5l+44lcHJUeO5N8/B/vyaDGgZZ7g59JKPVwCaqb2PGh YVfLVoUUwX6DpwtPunULwWAAe9X6G/7R5w== X-Google-Smtp-Source: AA6agR4bXd08YH1BOVWdTELnhwSN+hD1l+6TqksB579Elqzbv+Wg74BCw78fRSlkeEGnZWuD6CcH+A== X-Received: by 2002:a17:90b:1c85:b0:1f1:d78a:512b with SMTP id oo5-20020a17090b1c8500b001f1d78a512bmr10878742pjb.92.1659623338576; Thu, 04 Aug 2022 07:28:58 -0700 (PDT) Received: from localhost.localdomain ([122.162.196.218]) by smtp.gmail.com with ESMTPSA id h185-20020a6253c2000000b0052cdb06c125sm1013549pfb.159.2022.08.04.07.28.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Aug 2022 07:28:58 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, jorge.ramirez.ortiz@gmail.com, sjg@chromium.org, trini@konsulko.com, stephan@gerhold.net, mario.six@gdsys.cc, dsankouski@gmail.com, robert.marko@sartura.hr, luka.kovacic@sartura.hr, luka.perkov@sartura.hr, jh80.chung@samsung.com, nicolas.dechesne@linaro.org, vinod.koul@linaro.org, mworsfold@impinj.com, lgillham@impinj.com, daniel.thompson@linaro.org, pbrobinson@gmail.com, Sumit Garg Subject: [PATCH 10/13] gpio: qcom_pmic: Add support for GPIO LV/MV subtype Date: Thu, 4 Aug 2022 19:57:18 +0530 Message-Id: <20220804142721.536556-11-sumit.garg@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220804142721.536556-1-sumit.garg@linaro.org> References: <20220804142721.536556-1-sumit.garg@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean GPIO LV (low voltage)/MV (medium voltage) subtypes have different features and register mappings than 4CH/8CH subtypes. Add support for LV and MV subtypes. With GPIO LV/MV subtype available, add "qcom,pms405-gpio" compatible which requires support for GPIO MV subtype. Signed-off-by: Sumit Garg --- drivers/gpio/qcom_pmic_gpio.c | 96 +++++++++++++++++++++++++++-------- 1 file changed, 76 insertions(+), 20 deletions(-) diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index e9232a007f..3be1be8692 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -23,6 +23,15 @@ #define REG_TYPE 0x4 #define REG_SUBTYPE 0x5 +/* GPIO peripheral type and subtype out_values */ +#define REG_TYPE_VAL 0x10 +#define REG_SUBTYPE_GPIO_4CH 0x1 +#define REG_SUBTYPE_GPIOC_4CH 0x5 +#define REG_SUBTYPE_GPIO_8CH 0x9 +#define REG_SUBTYPE_GPIOC_8CH 0xd +#define REG_SUBTYPE_GPIO_LV 0x10 +#define REG_SUBTYPE_GPIO_MV 0x11 + #define REG_STATUS 0x08 #define REG_STATUS_VAL_MASK 0x1 @@ -33,6 +42,10 @@ #define REG_CTL_MODE_INOUT 0x20 #define REG_CTL_MODE_OUTPUT 0x10 #define REG_CTL_OUTPUT_MASK 0x0F +#define REG_CTL_LV_MV_MODE_MASK 0x3 +#define REG_CTL_LV_MV_MODE_INPUT 0x0 +#define REG_CTL_LV_MV_MODE_INOUT 0x2 +#define REG_CTL_LV_MV_MODE_OUTPUT 0x1 #define REG_DIG_VIN_CTL 0x41 #define REG_DIG_VIN_VIN0 0 @@ -40,6 +53,10 @@ #define REG_DIG_PULL_CTL 0x42 #define REG_DIG_PULL_NO_PU 0x5 +#define REG_LV_MV_OUTPUT_CTL 0x44 +#define REG_LV_MV_OUTPUT_CTL_MASK 0x80 +#define REG_LV_MV_OUTPUT_CTL_SHIFT 7 + #define REG_DIG_OUT_CTL 0x45 #define REG_DIG_OUT_CTL_CMOS (0x0 << 4) #define REG_DIG_OUT_CTL_DRIVE_L 0x1 @@ -49,6 +66,7 @@ struct qcom_gpio_bank { uint32_t pid; /* Peripheral ID on SPMI bus */ + bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */ }; static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset, @@ -56,6 +74,7 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset, { struct qcom_gpio_bank *priv = dev_get_priv(dev); uint32_t gpio_base = priv->pid + REG_OFFSET(offset); + uint32_t reg_ctl_val; int ret; /* Disable the GPIO */ @@ -64,16 +83,31 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset, if (ret < 0) return ret; - /* Select the mode */ - if (input) - ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL, - REG_CTL_MODE_INPUT); - else - ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL, - REG_CTL_MODE_INOUT | (value ? 1 : 0)); + /* Select the mode and output */ + if (priv->lv_mv_type) { + if (input) + reg_ctl_val = REG_CTL_LV_MV_MODE_INPUT; + else + reg_ctl_val = REG_CTL_LV_MV_MODE_INOUT; + } else { + if (input) + reg_ctl_val = REG_CTL_MODE_INPUT; + else + reg_ctl_val = REG_CTL_MODE_INOUT | !!value; + } + + ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL, reg_ctl_val); if (ret < 0) return ret; + if (priv->lv_mv_type && !input) { + ret = pmic_reg_write(dev->parent, + gpio_base + REG_LV_MV_OUTPUT_CTL, + !!value << REG_LV_MV_OUTPUT_CTL_SHIFT); + if (ret < 0) + return ret; + } + /* Set the right pull (no pull) */ ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_PULL_CTL, REG_DIG_PULL_NO_PU); @@ -118,19 +152,30 @@ static int qcom_gpio_get_function(struct udevice *dev, unsigned offset) uint32_t gpio_base = priv->pid + REG_OFFSET(offset); int reg; - /* Set the output value of the gpio */ reg = pmic_reg_read(dev->parent, gpio_base + REG_CTL); if (reg < 0) return reg; - switch (reg & REG_CTL_MODE_MASK) { - case REG_CTL_MODE_INPUT: - return GPIOF_INPUT; - case REG_CTL_MODE_INOUT: /* Fallthrough */ - case REG_CTL_MODE_OUTPUT: - return GPIOF_OUTPUT; - default: - return GPIOF_UNKNOWN; + if (priv->lv_mv_type) { + switch (reg & REG_CTL_LV_MV_MODE_MASK) { + case REG_CTL_LV_MV_MODE_INPUT: + return GPIOF_INPUT; + case REG_CTL_LV_MV_MODE_INOUT: /* Fallthrough */ + case REG_CTL_LV_MV_MODE_OUTPUT: + return GPIOF_OUTPUT; + default: + return GPIOF_UNKNOWN; + } + } else { + switch (reg & REG_CTL_MODE_MASK) { + case REG_CTL_MODE_INPUT: + return GPIOF_INPUT; + case REG_CTL_MODE_INOUT: /* Fallthrough */ + case REG_CTL_MODE_OUTPUT: + return GPIOF_OUTPUT; + default: + return GPIOF_UNKNOWN; + } } } @@ -154,8 +199,14 @@ static int qcom_gpio_set_value(struct udevice *dev, unsigned offset, uint32_t gpio_base = priv->pid + REG_OFFSET(offset); /* Set the output value of the gpio */ - return pmic_clrsetbits(dev->parent, gpio_base + REG_CTL, - REG_CTL_OUTPUT_MASK, !!value); + if (priv->lv_mv_type) + return pmic_clrsetbits(dev->parent, + gpio_base + REG_LV_MV_OUTPUT_CTL, + REG_LV_MV_OUTPUT_CTL_MASK, + !!value << REG_LV_MV_OUTPUT_CTL_SHIFT); + else + return pmic_clrsetbits(dev->parent, gpio_base + REG_CTL, + REG_CTL_OUTPUT_MASK, !!value); } static const struct dm_gpio_ops qcom_gpio_ops = { @@ -177,13 +228,17 @@ static int qcom_gpio_probe(struct udevice *dev) /* Do a sanity check */ reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE); - if (reg != 0x10) + if (reg != REG_TYPE_VAL) return log_msg_ret("bad type", -ENXIO); reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE); - if (reg != 0x5 && reg != 0x1) + if (reg != REG_SUBTYPE_GPIO_4CH && reg != REG_SUBTYPE_GPIOC_4CH && + reg != REG_SUBTYPE_GPIO_LV && reg != REG_SUBTYPE_GPIO_MV) return log_msg_ret("bad subtype", -ENXIO); + priv->lv_mv_type = reg == REG_SUBTYPE_GPIO_LV || + reg == REG_SUBTYPE_GPIO_MV; + return 0; } @@ -203,6 +258,7 @@ static const struct udevice_id qcom_gpio_ids[] = { { .compatible = "qcom,pm8916-gpio" }, { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ { .compatible = "qcom,pm8998-gpio" }, + { .compatible = "qcom,pms405-gpio" }, { } }; -- 2.25.1