From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CE2FCC19F2A for ; Thu, 4 Aug 2022 14:29:12 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5A83084856; Thu, 4 Aug 2022 16:28:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="Ip4D9IET"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 84AE68484F; Thu, 4 Aug 2022 16:28:33 +0200 (CEST) Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id DDCB184825 for ; Thu, 4 Aug 2022 16:28:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-pj1-x102c.google.com with SMTP id q7-20020a17090a7a8700b001f300db8677so5802934pjf.5 for ; Thu, 04 Aug 2022 07:28:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c9clITLruDMjvhmflOHHviOI+jVnFMTLiumVq3/LvEE=; b=Ip4D9IETsI+530uxK8lCaCdJJa1A/ikYlvx8vsGfLO0dNOydWMiodXpUXrrKqcH3qU 1mJr97Zb/z5JEb2oX6+kZsKYDwThcxlr/UDzydbq7u6MOOc4dQ+ezaE7UHvSZvQ1o15k RzRhlBA5VL07AOhjWiUMg1dBpjVDlsSX6CESsA0aHcSr2jsYhwUGNfjDTtmMbzt9WSbv YgBb3YgWg8NQI7pDMlTCuPJVG/0e6UJX6SdqTVQFhGcAScVRHeNniTn9gRsJ5rJvReDr vHimUHSWLsAOXelqGk9SQheLRa3wDgWFYknacMq7t1YokWxk3JNOtH9ILc5WCzjAQ35e Qflg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c9clITLruDMjvhmflOHHviOI+jVnFMTLiumVq3/LvEE=; b=ugAEN+0No98aW+ulz19GdrjugnxNfnUAa1bLjInBNlc6UjPPE1F4xNa9o+ivpLObAU ZMGe7UbgBo7FiphpboA7tkFixJlJ/j8Jn2wc9jmppmqN1L7OiTWQA7vBRWAFgdYezrHi knEh6156d4qHH0Tjx4H0WJnAHye30TZ3UL4dNAo7CyVn4RE53odq7Y5oGP3IDBeEQBZ8 +HUJh82lGZ1aKQvxq+FrkKfqRWaTCaIogtnB649ye2foGGuPWUpvBNNJs/9Y4iLsMWee jwroIJrrxzm90mlbR5KuEjD8qDjdfEuCS1qvg82Lv4or6hFKCocd7//Pbw+U8B51BQpN dp4g== X-Gm-Message-State: ACgBeo0yaR5xfET5omdCixWXGXKNaaIIvoYE4NdeDtlNzqeqqWBgb1ro uJDy5izC2FWbmzohwreANjDzTZ7nSYBwWg== X-Google-Smtp-Source: AA6agR6qsZe1EhJtc7aTTYsWq5uSKXYY3h/HwzcMgdQ7H0jfaHLbXBSK+fG1YXW4y4GJ1E1aRCShsA== X-Received: by 2002:a17:902:e804:b0:16f:4a25:b5be with SMTP id u4-20020a170902e80400b0016f4a25b5bemr2215695plg.171.1659623309077; Thu, 04 Aug 2022 07:28:29 -0700 (PDT) Received: from localhost.localdomain ([122.162.196.218]) by smtp.gmail.com with ESMTPSA id h185-20020a6253c2000000b0052cdb06c125sm1013549pfb.159.2022.08.04.07.28.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Aug 2022 07:28:28 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, jorge.ramirez.ortiz@gmail.com, sjg@chromium.org, trini@konsulko.com, stephan@gerhold.net, mario.six@gdsys.cc, dsankouski@gmail.com, robert.marko@sartura.hr, luka.kovacic@sartura.hr, luka.perkov@sartura.hr, jh80.chung@samsung.com, nicolas.dechesne@linaro.org, vinod.koul@linaro.org, mworsfold@impinj.com, lgillham@impinj.com, daniel.thompson@linaro.org, pbrobinson@gmail.com, Sumit Garg Subject: [PATCH 06/13] clocks: qcom: Add clock enable callback support Date: Thu, 4 Aug 2022 19:57:14 +0530 Message-Id: <20220804142721.536556-7-sumit.garg@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220804142721.536556-1-sumit.garg@linaro.org> References: <20220804142721.536556-1-sumit.garg@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Drivers like USB, ethernet etc. uses ".enable" hook to enable clocks. So add corresponding support for Qcom clock drivers. Signed-off-by: Sumit Garg --- arch/arm/mach-snapdragon/clock-apq8016.c | 5 +++++ arch/arm/mach-snapdragon/clock-apq8096.c | 5 +++++ arch/arm/mach-snapdragon/clock-qcs404.c | 5 +++++ arch/arm/mach-snapdragon/clock-sdm845.c | 5 +++++ arch/arm/mach-snapdragon/clock-snapdragon.c | 7 +++++++ 5 files changed, 27 insertions(+) diff --git a/arch/arm/mach-snapdragon/clock-apq8016.c b/arch/arm/mach-snapdragon/clock-apq8016.c index 6e4a0ccb90..23a37a1714 100644 --- a/arch/arm/mach-snapdragon/clock-apq8016.c +++ b/arch/arm/mach-snapdragon/clock-apq8016.c @@ -111,3 +111,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate) return 0; } } + +int msm_enable(struct clk *clk) +{ + return 0; +} diff --git a/arch/arm/mach-snapdragon/clock-apq8096.c b/arch/arm/mach-snapdragon/clock-apq8096.c index e5011be8f2..66184596d5 100644 --- a/arch/arm/mach-snapdragon/clock-apq8096.c +++ b/arch/arm/mach-snapdragon/clock-apq8096.c @@ -93,3 +93,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate) return 0; } } + +int msm_enable(struct clk *clk) +{ + return 0; +} diff --git a/arch/arm/mach-snapdragon/clock-qcs404.c b/arch/arm/mach-snapdragon/clock-qcs404.c index bb8a6fe067..230d7779a7 100644 --- a/arch/arm/mach-snapdragon/clock-qcs404.c +++ b/arch/arm/mach-snapdragon/clock-qcs404.c @@ -77,3 +77,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate) return 0; } + +int msm_enable(struct clk *clk) +{ + return 0; +} diff --git a/arch/arm/mach-snapdragon/clock-sdm845.c b/arch/arm/mach-snapdragon/clock-sdm845.c index f69be80898..d6df0365af 100644 --- a/arch/arm/mach-snapdragon/clock-sdm845.c +++ b/arch/arm/mach-snapdragon/clock-sdm845.c @@ -91,3 +91,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate) return 0; } } + +int msm_enable(struct clk *clk) +{ + return 0; +} diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index 5652d2fa36..fda7098274 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -20,6 +20,7 @@ #define CBCR_BRANCH_OFF_BIT BIT(31) extern ulong msm_set_rate(struct clk *clk, ulong rate); +extern int msm_enable(struct clk *clk); /* Enable clock controlled by CBC soft macro */ void clk_enable_cbc(phys_addr_t cbcr) @@ -126,8 +127,14 @@ static ulong msm_clk_set_rate(struct clk *clk, ulong rate) return msm_set_rate(clk, rate); } +static int msm_clk_enable(struct clk *clk) +{ + return msm_enable(clk); +} + static struct clk_ops msm_clk_ops = { .set_rate = msm_clk_set_rate, + .enable = msm_clk_enable, }; static const struct udevice_id msm_clk_ids[] = { -- 2.25.1