From: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
To: <u-boot@lists.denx.de>
Cc: <jagan@amarulasolutions.com>, <michal.simek@amd.com>,
<git@xilinx.com>, <git@amd.com>,
Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Subject: [PATCH 5/6] spi: zynqmp_qspi: Code alignment
Date: Thu, 25 Aug 2022 06:59:05 -0600 [thread overview]
Message-ID: <20220825125906.11581-6-ashok.reddy.soma@amd.com> (raw)
In-Reply-To: <20220825125906.11581-1-ashok.reddy.soma@amd.com>
Few lines are extented to next line though they can fit in 80 character
limit, align them to single line. No functional change.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
---
drivers/spi/zynqmp_gqspi.c | 18 ++++++------------
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index d5ccb48fde..4e718c545c 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -434,8 +434,7 @@ static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode)
debug("%s\n", __func__);
/* Set the SPI Clock phase and polarities */
confr = readl(®s->confr);
- confr &= ~(GQSPI_CONFIG_CPHA_MASK |
- GQSPI_CONFIG_CPOL_MASK);
+ confr &= ~(GQSPI_CONFIG_CPHA_MASK | GQSPI_CONFIG_CPOL_MASK);
if (mode & SPI_CPHA)
confr |= GQSPI_CONFIG_CPHA_MASK;
@@ -579,8 +578,7 @@ static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv)
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
- gen_fifo_cmd |= GQSPI_GFIFO_TX |
- GQSPI_GFIFO_DATA_XFR_MASK;
+ gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_GFIFO_DATA_XFR_MASK;
while (priv->len) {
len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
@@ -589,11 +587,9 @@ static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv)
debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd);
if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
- ret = zynqmp_qspi_fill_tx_fifo(priv,
- 1 << len);
+ ret = zynqmp_qspi_fill_tx_fifo(priv, 1 << len);
else
- ret = zynqmp_qspi_fill_tx_fifo(priv,
- len);
+ ret = zynqmp_qspi_fill_tx_fifo(priv, len);
if (ret)
return ret;
@@ -726,8 +722,7 @@ static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv)
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
- gen_fifo_cmd |= GQSPI_GFIFO_RX |
- GQSPI_GFIFO_DATA_XFR_MASK;
+ gen_fifo_cmd |= GQSPI_GFIFO_RX | GQSPI_GFIFO_DATA_XFR_MASK;
/*
* Check if receive buffer is aligned to 4 byte and length
@@ -742,8 +737,7 @@ static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv)
return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
}
- ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len,
- GQSPI_DMA_ALIGN));
+ ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len, GQSPI_DMA_ALIGN));
buf = (u32 *)tmp;
return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
}
--
2.17.1
next prev parent reply other threads:[~2022-08-25 13:00 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-25 12:59 [PATCH 0/6] zynqmp_gqspi driver updates Ashok Reddy Soma
2022-08-25 12:59 ` [PATCH 1/6] spi: zynqmp_gqspi: Add tap delays for Versal Ashok Reddy Soma
2022-08-25 12:59 ` [PATCH 2/6] arm64: versal: Define zynqmp_mmio_write() for versal Ashok Reddy Soma
2022-08-25 12:59 ` [PATCH 3/6] spi: zynqmp_gqspi: Add support for IO mode Ashok Reddy Soma
2022-08-25 12:59 ` [PATCH 4/6] spi: zynqmp_gqspi: Fix issue of reading more than 32bits length Ashok Reddy Soma
2022-08-25 12:59 ` Ashok Reddy Soma [this message]
2022-08-25 12:59 ` [PATCH 6/6] arm64: versal: Enable zynqmp_gqspi driver Ashok Reddy Soma
2022-09-06 7:30 ` [PATCH 0/6] zynqmp_gqspi driver updates Michal Simek
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