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X-IronPort-AV: E=Sophos;i="5.93,272,1654585200"; d="scan'208";a="171358876" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Aug 2022 23:20:36 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Sun, 28 Aug 2022 23:20:35 -0700 Received: from che-lt-i64410lx.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Sun, 28 Aug 2022 23:20:28 -0700 From: Balamanikandan Gunasundar To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH v2 7/9] ARM: dts: at91: sam9x60: Add nodes for EBI and NAND Date: Mon, 29 Aug 2022 11:49:26 +0530 Message-ID: <20220829061928.21895-8-balamanikandan.gunasundar@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220829061928.21895-1-balamanikandan.gunasundar@microchip.com> References: <20220829061928.21895-1-balamanikandan.gunasundar@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Add new bindings for EBI and NAND controller Signed-off-by: Balamanikandan Gunasundar --- arch/arm/dts/sam9x60.dtsi | 42 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi index a5c429eb3a..17224ef771 100644 --- a/arch/arm/dts/sam9x60.dtsi +++ b/arch/arm/dts/sam9x60.dtsi @@ -69,6 +69,32 @@ #size-cells = <1>; ranges; + ebi: ebi@10000000 { + compatible = "microchip,sam9x60-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&smc>; + microchip,sfr = <&sfr>; + reg = <0x10000000 0x60000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x20000000 0x10000000 + 0x2 0x0 0x30000000 0x10000000 + 0x3 0x0 0x40000000 0x10000000 + 0x4 0x0 0x50000000 0x10000000 + 0x5 0x0 0x60000000 0x10000000>; + clocks = <&pmc PMC_TYPE_CORE 11>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "microchip,sam9x60-nand-controller"; + ecc-engine = <&pmecc>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + sdhci0: sdhci-host@80000000 { compatible = "microchip,sam9x60-sdhci"; reg = <0x80000000 0x300>; @@ -119,6 +145,11 @@ status = "disabled"; }; + sfr: sfr@f8050000 { + compatible = "microchip,sam9x60-sfr", "syscon"; + reg = <0xf8050000 0x100>; + }; + dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; @@ -182,6 +213,17 @@ }; }; + pmecc: ecc-engine@ffffe000 { + compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc"; + reg = <0xffffe000 0x300>, + <0xffffe600 0x100>; + }; + + smc: smc@ffffea00 { + compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffea00 0x100>; + }; + pioA: gpio@fffff400 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; -- 2.34.1