From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B1B3DECAAA1 for ; Tue, 30 Aug 2022 11:33:10 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D302F84996; Tue, 30 Aug 2022 13:33:02 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="hAd0JNMx"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 5659584849; Tue, 30 Aug 2022 08:20:34 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7D25C84832 for ; Tue, 30 Aug 2022 08:20:31 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661840431; x=1693376431; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=u66YdOpRzplNAsvIA7o4NZSeTSb0tlrpLuoxF3tsZ6M=; b=hAd0JNMxTyvDblCWdAKvk6mjmVUw85Gt1mWbsO0767Ziv8qm1k486cCE U0zi/o4esnhkhRk471cqjTdY6sGRc9NEiDTUni7EP5/9q2AH2IOySEMHu 6r7SSV98YczuQgFian/ITVYlts7SMbY0vsyXzhRmF8mJBlnawRrsADmal 1dhpEZcX9fcDi0BHYMLD0qlYKmzmTiBPAgJUyQqKUlFdQNPX+oMs10JYz cBh0yE2UGD72pvoFzrzAG26WncQAVSJFkTXL7oS/MZz2DVEP9LjA4GO2L IBHraXTAz4LHTiWTS1/7+/pWYlkwxh++0BIbjR9Y6XBTToCbCgu8CXYJJ g==; X-IronPort-AV: E=McAfee;i="6500,9779,10454"; a="282064877" X-IronPort-AV: E=Sophos;i="5.93,274,1654585200"; d="scan'208";a="282064877" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2022 23:20:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,274,1654585200"; d="scan'208";a="737623398" Received: from pglmail07.png.intel.com ([10.221.193.207]) by orsmga004.jf.intel.com with ESMTP; 29 Aug 2022 23:20:24 -0700 Received: from localhost (pgli0078.png.intel.com [10.221.240.41]) by pglmail07.png.intel.com (Postfix) with ESMTP id 371202B06; Tue, 30 Aug 2022 14:20:24 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id 30333299B; Tue, 30 Aug 2022 14:20:24 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Chee Hong Ang Subject: [PATCH 016/347] FogBugz #516535: Fix QSPI write issues Date: Tue, 30 Aug 2022 14:20:09 +0800 Message-Id: <20220830062009.24408-1-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Tue, 30 Aug 2022 13:32:57 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Chee Hong Ang QSPI driver perform chip select on every flash read/write access. The driver need to disable/enable the QSPI controller while performing chip select. This may cause some data lost especially the QSPI controller is configured to run at slower speed as it may take longer time to access the flash device. This patch prevent the driver from disable/enable the QSPI controller too soon and inadvertently halting any ongoing flash read/write access by ensuring the QSPI controller is always in idle mode after each read/write access. Signed-off-by: Chee Hong Ang --- drivers/spi/cadence_qspi_apb.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 2cdf4c9c9f..5e03495f45 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -858,13 +858,9 @@ cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat *plat, writel(CQSPI_REG_INDIRECTRD_DONE, plat->regbase + CQSPI_REG_INDIRECTRD); - /* Check indirect done status */ - ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD, - CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0); - if (ret) { - printf("Indirect read clear completion error (%i)\n", ret); - goto failrd; - } + /* Wait til QSPI is idle */ + if (!cadence_qspi_wait_idle(plat->regbase)) + return -EIO; return 0; @@ -1031,6 +1027,11 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat, if (bounce_buf) free(bounce_buf); + + /* Wait til QSPI is idle */ + if (!cadence_qspi_wait_idle(plat->regbase)) + return -EIO; + return 0; failwr: -- 2.25.1