From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A3BD2ECAAD3 for ; Wed, 31 Aug 2022 07:25:17 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2A57784144; Wed, 31 Aug 2022 09:25:15 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=maquefel.me Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=maquefel.me header.i=@maquefel.me header.b="jfeUhhLy"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 6AD1680361; Wed, 31 Aug 2022 09:25:13 +0200 (CEST) Received: from forward503p.mail.yandex.net (forward503p.mail.yandex.net [77.88.28.113]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 57A6D80361 for ; Wed, 31 Aug 2022 09:25:10 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=maquefel.me Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=nikita.shubin@maquefel.me Received: from myt5-2f5ba0466eb8.qloud-c.yandex.net (myt5-2f5ba0466eb8.qloud-c.yandex.net [IPv6:2a02:6b8:c12:1c83:0:640:2f5b:a046]) by forward503p.mail.yandex.net (Yandex) with ESMTP id D5C1111010B3; Wed, 31 Aug 2022 10:25:07 +0300 (MSK) Received: by myt5-2f5ba0466eb8.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id PdXeeB9cuD-P6i0eRU7; Wed, 31 Aug 2022 10:25:06 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1661930706; bh=4eqDU4VjAbwnxD1IJeea3fKRHazh1f/AUSAv0FAwIv8=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=jfeUhhLyXMhLFd7FaZBq37U2oWQiVjbVLmeJyB4t3x/p/0BehIlMRqnE/jDusqptM /BLiuXaXOg+EIyv1AUsyIPTMpL1OBnReTCsrEKnEt67+OLmWLWwgR8WPrZR+ITf1IN +pHV2PnRaUNrGkE5nEMCzBpkb0M2WL6FQkOClcug= Authentication-Results: myt5-2f5ba0466eb8.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: u-boot@lists.denx.de Cc: linux@yadro.com, Nikita Shubin , Rick Chen , Leo , Simon Glass , Bin Meng , Heinrich Schuchardt , Ilias Apalodimas , Alexandru Gagniuc , Andrew Davis , Alper Nebi Yasak Subject: [PATCH v2] spl: introduce SPL_XIP to config Date: Wed, 31 Aug 2022 10:25:05 +0300 Message-Id: <20220831072505.8710-1-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.35.1 In-Reply-To: <30f43f76-d146-ea24-2dfd-a48197ad2839@gmail.com> References: <30f43f76-d146-ea24-2dfd-a48197ad2839@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Nikita Shubin U-Boot and SPL don't necessary share the same location, so we might end with U-Boot SPL in read-only memory (XIP) and U-Boot in read-write memory. In case of non XIP boot mode, we rely on such variables as "hart_lottery" and "available_harts_lock" which we use as atomics. The problem is that CONFIG_XIP also propagate to main U-Boot, not only SPL, so we need CONFIG_SPL_XIP to distinguish SPL XIP from other XIP modes. This adds an option special for SPL to behave it in XIP manner and we don't use hart_lottery and available_harts_lock, during start proccess. Signed-off-by: Nikita Shubin --- v1->v2: Sean Anderson: - used Kconfig description suggested by Sean - indeed more cleaner and understandable --- arch/riscv/cpu/cpu.c | 2 +- arch/riscv/cpu/start.S | 4 ++-- arch/riscv/include/asm/global_data.h | 2 +- arch/riscv/lib/asm-offsets.c | 2 +- arch/riscv/lib/smp.c | 2 +- common/spl/Kconfig | 7 +++++++ 6 files changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 9f5fa0bcb3..5d8163b19f 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -19,7 +19,7 @@ * The variables here must be stored in the data section since they are used * before the bss section is available. */ -#ifndef CONFIG_XIP +#if !CONFIG_IS_ENABLED(XIP) u32 hart_lottery __section(".data") = 0; /* diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index ac81783a90..c3c859e667 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -122,7 +122,7 @@ call_board_init_f_0: call_harts_early_init: jal harts_early_init -#ifndef CONFIG_XIP +#if !CONFIG_IS_ENABLED(XIP) /* * Pick hart to initialize global data and run U-Boot. The other harts * wait for initialization to complete. @@ -150,7 +150,7 @@ call_harts_early_init: /* save the boot hart id to global_data */ SREG tp, GD_BOOT_HART(gp) -#ifndef CONFIG_XIP +#if !CONFIG_IS_ENABLED(XIP) la t0, available_harts_lock amoswap.w.rl zero, zero, 0(t0) diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 9a146d1d49..a4d3cf430b 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -30,7 +30,7 @@ int iccm[CONFIG_NR_CPUS]; #if CONFIG_IS_ENABLED(SMP) struct ipi_data ipi[CONFIG_NR_CPUS]; #endif -#ifndef CONFIG_XIP +#if !CONFIG_IS_ENABLED(XIP) ulong available_harts; #endif }; diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c index f1fe089b3d..c4f48c8373 100644 --- a/arch/riscv/lib/asm-offsets.c +++ b/arch/riscv/lib/asm-offsets.c @@ -16,7 +16,7 @@ int main(void) { DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart)); DEFINE(GD_FIRMWARE_FDT_ADDR, offsetof(gd_t, arch.firmware_fdt_addr)); -#ifndef CONFIG_XIP +#if !CONFIG_IS_ENABLED(XIP) DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts)); #endif diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index ba992100ad..f8b756291f 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -45,7 +45,7 @@ static int send_ipi_many(struct ipi_data *ipi, int wait) continue; } -#ifndef CONFIG_XIP +#if !CONFIG_IS_ENABLED(XIP) /* skip if hart is not available */ if (!(gd->arch.available_harts & (1 << reg))) continue; diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 07c03d611d..777eff5e47 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -27,6 +27,13 @@ config SPL_FRAMEWORK supports MMC, NAND and YMODEM and other methods loading of U-Boot and the Linux Kernel. If unsure, say Y. +config SPL_XIP + bool "Enable XIP mode for SPL" + help + Support booting SPL from read-only memory (such as XIP). Don't rely on + lock variables (for example hart_lottery and available_harts_lock) + since they cannot be modified. + config SPL_FRAMEWORK_BOARD_INIT_F bool "Define a generic function board_init_f" depends on SPL_FRAMEWORK -- 2.35.1