From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B82FC54EE9 for ; Fri, 2 Sep 2022 08:42:41 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B021481FD2; Fri, 2 Sep 2022 10:42:38 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=maquefel.me Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=maquefel.me header.i=@maquefel.me header.b="FLZFlkRE"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 76F3E84A51; Fri, 2 Sep 2022 10:42:36 +0200 (CEST) Received: from forward503o.mail.yandex.net (forward503o.mail.yandex.net [37.140.190.205]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5AED683FF4 for ; Fri, 2 Sep 2022 10:42:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=maquefel.me Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=nikita.shubin@maquefel.me Received: from vla5-91e5293da019.qloud-c.yandex.net (vla5-91e5293da019.qloud-c.yandex.net [IPv6:2a02:6b8:c18:3e1f:0:640:91e5:293d]) by forward503o.mail.yandex.net (Yandex) with ESMTP id 42ABB5C4E74; Fri, 2 Sep 2022 11:42:25 +0300 (MSK) Received: by vla5-91e5293da019.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id sPmOHYiBSy-gNfOHcIQ; Fri, 02 Sep 2022 11:42:24 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1662108144; bh=m5MLZjwCvuB2A6ECrlilxYs2dftHwhgWqlMhTGWMPTU=; h=Cc:Message-ID:Subject:Date:References:To:From:In-Reply-To; b=FLZFlkREmJSPZqvGrbOjEH3Jsa2I5FDPNYPoVM5qVdgFIZNIKQ6jBWIV2gwhgncqu hZ4I0Wvs3LlpCtzSfIWl2qHOv+Bzs945UEAn8oy22pDDPcow0Bo+84yn7zO8VYGdEz 8PbBovoDodJCt324WCGGYwfjQoEEICcAw+/TH/jM= Authentication-Results: vla5-91e5293da019.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me Date: Fri, 2 Sep 2022 11:42:22 +0300 From: Nikita Shubin To: Rick Chen Cc: U-Boot Mailing List , linux@yadro.com, Leo Liang , Simon Glass , Bin Meng , Heinrich Schuchardt , ilias.apalodimas@linaro.org, mr.nuke.me@gmail.com, afd@ti.com, alpernebiyasak@gmail.com Subject: Re: [PATCH v2] spl: introduce SPL_XIP to config Message-ID: <20220902114222.637b470c@redslave.neermore.group> In-Reply-To: References: <30f43f76-d146-ea24-2dfd-a48197ad2839@gmail.com> <20220831072505.8710-1-nikita.shubin@maquefel.me> X-Mailer: Claws Mail 3.17.7 (GTK+ 2.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Fri, 2 Sep 2022 15:25:06 +0800 Rick Chen wrote: Hello Rick! > Hi Nikita, >=20 > > From: Nikita Shubin > > Sent: Wednesday, August 31, 2022 3:25 PM > > To: u-boot@lists.denx.de > > Cc: linux@yadro.com; Nikita Shubin ; Rick > > Jian-Zhi Chen(=E9=99=B3=E5=BB=BA=E5=BF=97) ; Leo Yu= -Chi > > Liang(=E6=A2=81=E8=82=B2=E9=BD=8A) ; Simon Glass > > ; Bin Meng ; Heinrich > > Schuchardt ; Ilias Apalodimas > > ; Alexandru Gagniuc > > ; Andrew Davis ; Alper Nebi Yasak > > Subject: [PATCH v2] spl: introduce > > SPL_XIP to config > > > > From: Nikita Shubin > > > > U-Boot and SPL don't necessary share the same location, so we might > > end with U-Boot SPL in read-only memory (XIP) and U-Boot in > > read-write memory. > > > > In case of non XIP boot mode, we rely on such variables as > > "hart_lottery" and "available_harts_lock" which we use as atomics. > > > > The problem is that CONFIG_XIP also propagate to main U-Boot, not > > only SPL, so we need CONFIG_SPL_XIP to distinguish SPL XIP from > > other XIP modes. > > > > This adds an option special for SPL to behave it in XIP manner and > > we don't use hart_lottery and available_harts_lock, during start > > proccess. > > > > Signed-off-by: Nikita Shubin > > --- > > v1->v2: > > Sean Anderson: > > - used Kconfig description suggested by Sean - indeed more > > cleaner and understandable --- > > arch/riscv/cpu/cpu.c | 2 +- > > arch/riscv/cpu/start.S | 4 ++-- > > arch/riscv/include/asm/global_data.h | 2 +- > > arch/riscv/lib/asm-offsets.c | 2 +- > > arch/riscv/lib/smp.c | 2 +- > > common/spl/Kconfig | 7 +++++++ > > 6 files changed, 13 insertions(+), 6 deletions(-) > > > > diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index > > 9f5fa0bcb3..5d8163b19f 100644 --- a/arch/riscv/cpu/cpu.c > > +++ b/arch/riscv/cpu/cpu.c > > @@ -19,7 +19,7 @@ > > * The variables here must be stored in the data section since > > they are used > > * before the bss section is available. > > */ > > -#ifndef CONFIG_XIP > > +#if !CONFIG_IS_ENABLED(XIP) > > u32 hart_lottery __section(".data") =3D 0; > > > > /* > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index > > ac81783a90..c3c859e667 100644 --- a/arch/riscv/cpu/start.S > > +++ b/arch/riscv/cpu/start.S > > @@ -122,7 +122,7 @@ call_board_init_f_0: > > call_harts_early_init: > > jal harts_early_init > > > > -#ifndef CONFIG_XIP > > +#if !CONFIG_IS_ENABLED(XIP) > > /* > > * Pick hart to initialize global data and run U-Boot. The > > other harts > > * wait for initialization to complete. > > @@ -150,7 +150,7 @@ call_harts_early_init: > > /* save the boot hart id to global_data */ > > SREG tp, GD_BOOT_HART(gp) > > > > -#ifndef CONFIG_XIP > > +#if !CONFIG_IS_ENABLED(XIP) > > la t0, available_harts_lock > > amoswap.w.rl zero, zero, 0(t0) > > > > diff --git a/arch/riscv/include/asm/global_data.h > > b/arch/riscv/include/asm/global_data.h index 9a146d1d49..a4d3cf430b > > 100644 --- a/arch/riscv/include/asm/global_data.h > > +++ b/arch/riscv/include/asm/global_data.h > > @@ -30,7 +30,7 @@ int iccm[CONFIG_NR_CPUS]; #if > > CONFIG_IS_ENABLED(SMP) struct ipi_data ipi[CONFIG_NR_CPUS]; > > #endif > > -#ifndef CONFIG_XIP > > +#if !CONFIG_IS_ENABLED(XIP) > > ulong available_harts; > > #endif > > }; > > diff --git a/arch/riscv/lib/asm-offsets.c > > b/arch/riscv/lib/asm-offsets.c index f1fe089b3d..c4f48c8373 100644 > > --- a/arch/riscv/lib/asm-offsets.c +++ > > b/arch/riscv/lib/asm-offsets.c @@ -16,7 +16,7 @@ int main(void) > > { > > DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart)); > > DEFINE(GD_FIRMWARE_FDT_ADDR, offsetof(gd_t, > > arch.firmware_fdt_addr)); -#ifndef CONFIG_XIP +#if > > !CONFIG_IS_ENABLED(XIP) DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, > > arch.available_harts)); #endif > > > > diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index > > ba992100ad..f8b756291f 100644 --- a/arch/riscv/lib/smp.c > > +++ b/arch/riscv/lib/smp.c > > @@ -45,7 +45,7 @@ static int send_ipi_many(struct ipi_data *ipi, > > int wait) continue; > > } > > > > -#ifndef CONFIG_XIP > > +#if !CONFIG_IS_ENABLED(XIP) > > /* skip if hart is not available */ > > if (!(gd->arch.available_harts & (1 << reg))) > > continue; > > diff --git a/common/spl/Kconfig b/common/spl/Kconfig index > > 07c03d611d..777eff5e47 100644 --- a/common/spl/Kconfig > > +++ b/common/spl/Kconfig > > @@ -27,6 +27,13 @@ config SPL_FRAMEWORK > > supports MMC, NAND and YMODEM and other methods loading > > of U-Boot and the Linux Kernel. If unsure, say Y. > > =20 >=20 > Would you please move the below SPL_XIP to arch/riscv/Kconfig and > aside the CONFIG_XIP. > Since hart_lottery and available_harts_lock only be used by RISC-V > currently. >=20 > And also please help to change CONFIG_XIP to CONFIG_SPL_XIP in the > following defconfig, or the behavior will be unexpected for AE350. > ./ae350_rv64_spl_xip_defconfig:CONFIG_XIP=3Dy > ./ae350_rv32_spl_xip_defconfig:CONFIG_XIP=3Dy >=20 No problem. Thanks for catching ae350. > Other looks great for me. >=20 > Thanks, > Rick >=20 > > +config SPL_XIP > > + bool "Enable XIP mode for SPL" > > + help > > + Support booting SPL from read-only memory (such as XIP). > > Don't rely on > > + lock variables (for example hart_lottery and > > available_harts_lock) > > + since they cannot be modified. > > + > > config SPL_FRAMEWORK_BOARD_INIT_F > > bool "Define a generic function board_init_f" > > depends on SPL_FRAMEWORK > > -- > > 2.35.1 =20