u-boot.lists.denx.de archive mirror
 help / color / mirror / Atom feed
From: Andre Przywara <andre.przywara@arm.com>
To: Samuel Holland <samuel@sholland.org>,
	Jagan Teki <jagan@amarulasolutions.com>
Cc: u-boot@lists.denx.de, Icenowy Zheng <uwu@icenowy.me>,
	Jernej Skrabec <jernej.skrabec@gmail.com>
Subject: [RFC PATCH 13/17] sunxi: add early Allwinner R528/T113 SoC support
Date: Tue,  6 Dec 2022 00:45:45 +0000	[thread overview]
Message-ID: <20221206004549.29015-14-andre.przywara@arm.com> (raw)
In-Reply-To: <20221206004549.29015-1-andre.przywara@arm.com>

This adds the remaining code bits to teach U-Boot about Allwinner's
newest SoC generation. This was introduced with the RISC-V based
Allwinner D1 SoC, which actually shares a die with the ARM cores versions
called R528 (BGA, without DRAM) and T113s (QFP, with embedded DRAM).

This adds the new Kconfig stanza, using the two newly introduced symbols
for the new SoC generation and pincontroller. It also adds the new symbols
to the relavent code places, to set all the hardcoded bits directly.

We just chicken out the DRAM controller code for now with a stub to make
it compile. There is GPLed code out there that can be used, although that
still looks very much like the disassembly/decompile it came from.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 .../arm/include/asm/arch-sunxi/clock_sun50i_h6.h |  5 +++++
 arch/arm/mach-sunxi/Kconfig                      | 16 ++++++++++++++++
 arch/arm/mach-sunxi/board.c                      |  4 ++++
 arch/arm/mach-sunxi/clock_sun50i_h6.c            |  2 ++
 arch/arm/mach-sunxi/cpu_info.c                   |  2 ++
 board/sunxi/Makefile                             |  1 +
 board/sunxi/dram_sun8i_r528.c                    |  9 +++++++++
 drivers/mmc/sunxi_mmc.c                          |  1 +
 drivers/pinctrl/sunxi/Kconfig                    |  1 +
 9 files changed, 41 insertions(+)
 create mode 100644 board/sunxi/dram_sun8i_r528.c

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
index 8471e11aa02..d34a9baf5e1 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -288,6 +288,11 @@ struct sunxi_ccm_reg {
 
 /* apb1 bit field */
 #define CCM_APB1_DEFAULT		0x03000102
+#elif CONFIG_MACH_SUN8I_R528
+#define CCM_PLL6_DEFAULT		0xe8216300
+#define CCM_PSI_AHB1_AHB2_DEFAULT	0x03000002
+//#define CCM_AHB3_DEFAULT		0x03000002
+#define CCM_APB1_DEFAULT		0x03000102
 #endif
 
 /* apb2 bit field */
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index b59db212fa8..71799686a05 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -51,6 +51,12 @@ config DRAM_SUN50I_H616
 	  Select this dram controller driver for some sun50i platforms,
 	  like H616.
 
+config DRAM_SUN8I_R528
+	bool
+	help
+	  Select this DRAM controller driver for the R528, T113, D1
+	  and D1s/F133 SoC.
+
 if DRAM_SUN50I_H616
 config DRAM_SUN50I_H616_WRITE_LEVELING
 	bool "H616 DRAM write leveling"
@@ -318,6 +324,15 @@ config MACH_SUN8I_R40
 	select PHY_SUN4I_USB
 	imply SPL_SYS_I2C_LEGACY
 
+config MACH_SUN8I_R528
+	bool "sun8i (Allwinner R528)"
+	select CPU_V7A
+	select SUNXI_GEN_NCAT2
+	select SUNXI_NEW_PINCTRL
+	select MMC_SUNXI_HAS_NEW_MODE
+	select SUPPORT_SPL
+	select DRAM_SUN8I_R528
+
 config MACH_SUN8I_V3S
 	bool "sun8i (Allwinner V3/V3s/S3/S3L)"
 	select CPU_V7A
@@ -622,6 +637,7 @@ config SYS_CONFIG_NAME
 	default "sun6i" if MACH_SUN6I
 	default "sun7i" if MACH_SUN7I
 	default "sun8i" if MACH_SUN8I
+	default "sun8i" if MACH_SUN8I_R528
 	default "sun9i" if MACH_SUN9I
 	default "sun50i" if MACH_SUN50I
 	default "sun50i" if MACH_SUN50I_H6
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 3763ec3d2e4..33331cda5e2 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -148,6 +148,10 @@ static int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_R528)
+	sunxi_gpio_set_cfgpin(SUNXI_GPE(2), 6);
+	sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 6);
+	sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV)
 	sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0);
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index 607efe6a9c1..4d5e23a9af4 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -38,7 +38,9 @@ void clock_init_safe(void)
 			CCM_CPU_AXI_DEFAULT_FACTORS);
 
 	writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg);
+#ifdef CCM_AHB3_DEFAULT
 	writel(CCM_AHB3_DEFAULT, &ccm->ahb3_cfg);
+#endif
 	writel(CCM_APB1_DEFAULT, &ccm->apb1_cfg);
 
 	/*
diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
index 7eef178859b..7fecc3b88dd 100644
--- a/arch/arm/mach-sunxi/cpu_info.c
+++ b/arch/arm/mach-sunxi/cpu_info.c
@@ -93,6 +93,8 @@ int print_cpuinfo(void)
 	printf("CPU:   Allwinner R40 (SUN8I %04x)\n", sunxi_get_sram_id());
 #elif defined CONFIG_MACH_SUN8I_V3S
 	printf("CPU:   Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id());
+#elif defined CONFIG_MACH_SUN8I_R528
+	puts("CPU:   Allwinner R528 (SUN8I)\n");
 #elif defined CONFIG_MACH_SUN9I
 	puts("CPU:   Allwinner A80 (SUN9I)\n");
 #elif defined CONFIG_MACH_SUN50I
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index 7763b032c80..db16cf247c6 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -12,4 +12,5 @@ obj-$(CONFIG_SUN7I_GMAC)	+= gmac.o
 obj-$(CONFIG_MACH_SUN4I)	+= dram_sun4i_auto.o
 obj-$(CONFIG_MACH_SUN5I)	+= dram_sun5i_auto.o
 obj-$(CONFIG_MACH_SUN7I)	+= dram_sun5i_auto.o
+obj-$(CONFIG_DRAM_SUN8I_R528)	+= dram_sun8i_r528.o
 obj-$(CONFIG_CHIP_DIP_SCAN)	+= chip.o
diff --git a/board/sunxi/dram_sun8i_r528.c b/board/sunxi/dram_sun8i_r528.c
new file mode 100644
index 00000000000..84261df1cd8
--- /dev/null
+++ b/board/sunxi/dram_sun8i_r528.c
@@ -0,0 +1,9 @@
+/*
+ * Quick hack to make it compile, we cannot use the SPL just yet.
+ * There is GPLed DRAM code in awboot, to be lifted here, after some
+ * massaging.
+ */
+unsigned long sunxi_dram_init(void)
+{
+	return 128 * 1024 * 1024;
+}
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 6ce2729473c..59b1bbd4a9c 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -736,6 +736,7 @@ static const struct udevice_id sunxi_mmc_ids[] = {
 	{ .compatible = "allwinner,sun50i-h6-emmc" },
 	{ .compatible = "allwinner,sun50i-a100-mmc" },
 	{ .compatible = "allwinner,sun50i-a100-emmc" },
+	{ .compatible = "allwinner,sun20i-d1-mmc" },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index c8f937d91e9..cbd61795986 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -126,6 +126,7 @@ config PINCTRL_SUN50I_H616_R
 
 config PINCTRL_SUN20I_D1
 	bool "Support for the Allwinner D1/R528 PIO"
+	default MACH_SUN8I_R528
 	select PINCTRL_SUNXI
 
 endif
-- 
2.35.5


  parent reply	other threads:[~2022-12-06  0:50 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 01/17] sunxi: remove CONFIG_SATAPWR Andre Przywara
2022-12-14  8:37   ` Samuel Holland
2022-12-14 14:25     ` Andre Przywara
2022-12-14 23:40       ` Samuel Holland
2022-12-06  0:45 ` [RFC PATCH 02/17] sunxi: remove CONFIG_MACPWR Andre Przywara
2022-12-14  9:09   ` Samuel Holland
2022-12-14 14:23     ` Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 03/17] pinctrl: sunxi: remove struct sunxi_gpio Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 04/17] pinctrl: sunxi: add GPIO in/out wrappers Andre Przywara
2022-12-15  5:59   ` Samuel Holland
2022-12-06  0:45 ` [RFC PATCH 05/17] pinctrl: sunxi: move pinctrl code and remove GPIO_EXTRA_HEADER Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 06/17] pinctrl: sunxi: move PIO_BASE into sunxi_gpio.h Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 07/17] pinctrl: sunxi: add new D1 pinctrl support Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model Andre Przywara
2022-12-06  5:38   ` Icenowy Zheng
2023-05-16  2:32   ` Sam Edwards
2023-05-16 21:08     ` Andre Przywara
2023-05-16 23:53       ` Sam Edwards
2023-05-17  0:43         ` Andre Przywara
2023-05-17  8:56           ` Andre Przywara
2023-05-17 14:04             ` Maxim Kiselev
2023-05-25 18:25               ` Maksim Kiselev
2023-05-26 11:05                 ` Andre Przywara
2023-06-03 18:03   ` Sam Edwards
2022-12-06  0:45 ` [RFC PATCH 09/17] pinctrl: sunxi: add Allwinner D1 pinctrl description Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU Andre Przywara
2023-05-22  3:57   ` Sam Edwards
2023-05-24  0:58     ` Andre Przywara
2023-05-26  0:34   ` Sam Edwards
2023-05-26 10:50     ` Andre Przywara
2023-05-26 19:27       ` Maksim Kiselev
2023-05-26 20:22         ` Sam Edwards
2023-05-26 22:07           ` Andre Przywara
2023-05-27  2:15             ` Sam Edwards
2023-05-30  0:58               ` Sam Edwards
2023-05-31 15:19                 ` Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 11/17] sunxi: clock: D1/R528: Enable PLL LDO during PLL1 setup Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 12/17] sunxi: clock: support D1/R528 PLL6 clock Andre Przywara
2022-12-06  0:45 ` Andre Przywara [this message]
2023-05-16  2:52   ` [RFC PATCH 13/17] sunxi: add early Allwinner R528/T113 SoC support Sam Edwards
2023-05-16 22:01     ` Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 14/17] sunxi: refactor serial base addresses to avoid asm/arch/cpu.h Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 15/17] riscv: dts: allwinner: Add the D1/D1s SoC devicetree Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 16/17] arm: sunxi: add Allwinner T113s devicetree stub Andre Przywara
2022-12-06  5:55   ` Icenowy Zheng
2023-01-03 17:38     ` Andre Przywara
2023-01-04  5:49       ` Icenowy Zheng
2022-12-06  0:45 ` [RFC PATCH 17/17] sunxi: add preliminary MangoPi MQ-R board support Andre Przywara
2023-06-09 22:16 ` [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Sam Edwards
2023-06-12  0:20   ` Andre Przywara
2023-06-12 21:18     ` Sam Edwards
2023-06-15  0:07       ` Andre Przywara
2023-06-18 19:01         ` Sam Edwards
2023-06-20 12:42           ` Andre Przywara
2023-06-20 22:11             ` Sam Edwards
2023-06-21 10:55               ` Andre Przywara
2023-06-21 20:22                 ` Sam Edwards
2023-06-16 15:59       ` Andre Przywara
2023-06-16 16:27         ` Maxim Kiselev
2023-06-16 16:36           ` Andre Przywara
2023-06-17  8:26             ` Maxim Kiselev

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20221206004549.29015-14-andre.przywara@arm.com \
    --to=andre.przywara@arm.com \
    --cc=jagan@amarulasolutions.com \
    --cc=jernej.skrabec@gmail.com \
    --cc=samuel@sholland.org \
    --cc=u-boot@lists.denx.de \
    --cc=uwu@icenowy.me \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).