From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2EE1C7618A for ; Sun, 19 Mar 2023 17:13:31 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C16BE85D4B; Sun, 19 Mar 2023 18:10:48 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=mailbox.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; secure) header.d=mailbox.org header.i=@mailbox.org header.b="syBBkFwK"; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="V+gGnsXN"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4EAB4839AD; Sun, 19 Mar 2023 18:07:50 +0100 (CET) Received: from mout-p-103.mailbox.org (mout-p-103.mailbox.org [80.241.56.161]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 47E0C85D39 for ; Sun, 19 Mar 2023 18:07:09 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=mailbox.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=marek.vasut+renesas@mailbox.org Received: from smtp2.mailbox.org (smtp2.mailbox.org [IPv6:2001:67c:2050:b231:465::2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-103.mailbox.org (Postfix) with ESMTPS id 4Pfkn66lsMz9sQP; Sun, 19 Mar 2023 18:07:06 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1679245627; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lqrd5k0QhBRw/KLBy+tdBtVDzzVFvNrBxqrHwtw9rWQ=; b=syBBkFwK6S47EXLKMhsuSDD+TFoC0/hXmqD3kvVh/5LqgvOiZDv/LAmYlcbMX0vSVtVTej zMlPDT+9FuT4Jb6KQu9jRaEzHDkWkSpL64X+WLSpBy49QNVWCrMn/a/13Bpp+z8Dz47OLJ ZzzATmXOSevwtVo3H61KED1nvlx2KzL87GSZ/e+cGPJDZF8+F7hHFVwKAvVeeqs0q6B5Gq yDw+HlvPVIqdMvU8OYrUbo8gTloK/0gavGjS03UkCyKoSXWGjaUIqq1rIQjx7ioCY4M94g kxW715c24gPdVaEvoIjAWsJa00zBWkdKFGyhTCZXENhscXrisXxWyAYZo2YruA== From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1679245624; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lqrd5k0QhBRw/KLBy+tdBtVDzzVFvNrBxqrHwtw9rWQ=; b=V+gGnsXN014PfJG7sGIgTxxcj8PeYI2OyeVNF2OrjFM3eZl66WjpAccASCpc3wXYYpoEIL Bk0KjHKUAuqy+pcUry8xYinwKlLJHSI1BihOrUUe4PbbhEiAzBAfv7fkit8ahFYDxFHpAv d1fOhSI4WTybh4uT4kfCxw6xHgT5WSZPo4Qgw6Rywu3bw4mP9qRFZlgh1XkxT/JE/AuwMG 7c9ieLvbwZwjGqlfsQyvAzHPguKjULE39bShMtc9eEIrYOBnKmvnG5DZrYBgDpdiUUQEmo aPLefALrSgZc7vqvQysGwQ+eWHM5pb8poHFCPwV1lR51usbYdYvX9F/XiWXxqw== To: u-boot@lists.denx.de Cc: Marek Vasut , "Ariel D'Alessandro" , =?UTF-8?q?Marek=20Beh=C3=BAn?= , Joe Hershberger , Ramon Fried , Stefan Roese , Tim Harvey , Vladimir Oltean Subject: [PATCH 3/3] net: phy: Synchronize PHY interface modes with Linux Date: Sun, 19 Mar 2023 18:06:47 +0100 Message-Id: <20230319170647.28149-3-marek.vasut+renesas@mailbox.org> In-Reply-To: <20230319170647.28149-1-marek.vasut+renesas@mailbox.org> References: <20230319170647.28149-1-marek.vasut+renesas@mailbox.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-MBO-RS-ID: 9be8be9831388bbf201 X-MBO-RS-META: txhhbdtosckpn8ptr4z8ysu3x8d557fd X-Rspamd-Queue-Id: 4Pfkn66lsMz9sQP X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Synchronize PHY interface modes with Linux next 6.2.y commit: 0194b64578e90 ("net: phy: improve phy_read_poll_timeout") Retain LX2160A/LX2162A PHY modes as those are not yet supported by the Linux kernel, but isolate those with ifdeffery. Isolate NCSI which are also not supported by Linux kernel. Note that the ifdeffery cannot be avoided with IS_ENABLED() here due to compilation of the entire conditional, which would fail in case NCSI symbols are not available. Signed-off-by: Marek Vasut --- Cc: "Ariel D'Alessandro" Cc: "Marek Behún" Cc: Joe Hershberger Cc: Marek Vasut Cc: Ramon Fried Cc: Stefan Roese Cc: Tim Harvey Cc: Vladimir Oltean --- drivers/net/phy/phy.c | 4 +++ include/phy_interface.h | 68 +++++++++++++++++++++++++++++------------ 2 files changed, 53 insertions(+), 19 deletions(-) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 9b0e497f223..f720d0a7920 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -1160,7 +1160,11 @@ int phy_clear_bits_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val bool phy_interface_is_ncsi(void) { +#ifdef CONFIG_PHY_NCSI struct eth_pdata *pdata = dev_get_plat(eth_get_dev()); return pdata->phy_interface == PHY_INTERFACE_MODE_NCSI; +#else + return 0; +#endif } diff --git a/include/phy_interface.h b/include/phy_interface.h index 52af7e612b6..31be3228c7c 100644 --- a/include/phy_interface.h +++ b/include/phy_interface.h @@ -14,65 +14,95 @@ typedef enum { PHY_INTERFACE_MODE_NA, /* don't touch */ + PHY_INTERFACE_MODE_INTERNAL, PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_SGMII, - PHY_INTERFACE_MODE_SGMII_2500, - PHY_INTERFACE_MODE_QSGMII, PHY_INTERFACE_MODE_TBI, + PHY_INTERFACE_MODE_REVMII, PHY_INTERFACE_MODE_RMII, + PHY_INTERFACE_MODE_REVRMII, PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_RGMII_ID, PHY_INTERFACE_MODE_RGMII_RXID, PHY_INTERFACE_MODE_RGMII_TXID, PHY_INTERFACE_MODE_RTBI, + PHY_INTERFACE_MODE_SMII, + PHY_INTERFACE_MODE_XGMII, + PHY_INTERFACE_MODE_XLGMII, + PHY_INTERFACE_MODE_MOCA, + PHY_INTERFACE_MODE_QSGMII, + PHY_INTERFACE_MODE_TRGMII, + PHY_INTERFACE_MODE_100BASEX, PHY_INTERFACE_MODE_1000BASEX, PHY_INTERFACE_MODE_2500BASEX, - PHY_INTERFACE_MODE_XGMII, - PHY_INTERFACE_MODE_XAUI, - PHY_INTERFACE_MODE_RXAUI, PHY_INTERFACE_MODE_5GBASER, - PHY_INTERFACE_MODE_SFI, - PHY_INTERFACE_MODE_INTERNAL, + PHY_INTERFACE_MODE_RXAUI, + PHY_INTERFACE_MODE_XAUI, + /* 10GBASE-R, XFI, SFI - single lane 10G Serdes */ + PHY_INTERFACE_MODE_10GBASER, + PHY_INTERFACE_MODE_25GBASER, + PHY_INTERFACE_MODE_USXGMII, + /* 10GBASE-KR - with Clause 73 AN */ + PHY_INTERFACE_MODE_10GKR, + PHY_INTERFACE_MODE_QUSGMII, + PHY_INTERFACE_MODE_1000BASEKX, +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) + /* LX2160A SERDES modes */ PHY_INTERFACE_MODE_25G_AUI, PHY_INTERFACE_MODE_XLAUI, PHY_INTERFACE_MODE_CAUI2, PHY_INTERFACE_MODE_CAUI4, +#endif +#if defined(CONFIG_PHY_NCSI) PHY_INTERFACE_MODE_NCSI, - PHY_INTERFACE_MODE_10GBASER, - PHY_INTERFACE_MODE_USXGMII, +#endif PHY_INTERFACE_MODE_MAX, } phy_interface_t; static const char * const phy_interface_strings[] = { - [PHY_INTERFACE_MODE_NA] = "", + [PHY_INTERFACE_MODE_NA] = "", + [PHY_INTERFACE_MODE_INTERNAL] = "internal", [PHY_INTERFACE_MODE_MII] = "mii", [PHY_INTERFACE_MODE_GMII] = "gmii", [PHY_INTERFACE_MODE_SGMII] = "sgmii", - [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500", - [PHY_INTERFACE_MODE_QSGMII] = "qsgmii", [PHY_INTERFACE_MODE_TBI] = "tbi", + [PHY_INTERFACE_MODE_REVMII] = "rev-mii", [PHY_INTERFACE_MODE_RMII] = "rmii", + [PHY_INTERFACE_MODE_REVRMII] = "rev-rmii", [PHY_INTERFACE_MODE_RGMII] = "rgmii", [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id", [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid", [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid", [PHY_INTERFACE_MODE_RTBI] = "rtbi", + [PHY_INTERFACE_MODE_SMII] = "smii", + [PHY_INTERFACE_MODE_XGMII] = "xgmii", + [PHY_INTERFACE_MODE_XLGMII] = "xlgmii", + [PHY_INTERFACE_MODE_MOCA] = "moca", + [PHY_INTERFACE_MODE_QSGMII] = "qsgmii", + [PHY_INTERFACE_MODE_TRGMII] = "trgmii", [PHY_INTERFACE_MODE_1000BASEX] = "1000base-x", + [PHY_INTERFACE_MODE_1000BASEKX] = "1000base-kx", [PHY_INTERFACE_MODE_2500BASEX] = "2500base-x", - [PHY_INTERFACE_MODE_XGMII] = "xgmii", - [PHY_INTERFACE_MODE_XAUI] = "xaui", - [PHY_INTERFACE_MODE_RXAUI] = "rxaui", [PHY_INTERFACE_MODE_5GBASER] = "5gbase-r", - [PHY_INTERFACE_MODE_SFI] = "sfi", - [PHY_INTERFACE_MODE_INTERNAL] = "internal", + [PHY_INTERFACE_MODE_RXAUI] = "rxaui", + [PHY_INTERFACE_MODE_XAUI] = "xaui", + [PHY_INTERFACE_MODE_10GBASER] = "10gbase-r", + [PHY_INTERFACE_MODE_25GBASER] = "25gbase-r", + [PHY_INTERFACE_MODE_USXGMII] = "usxgmii", + [PHY_INTERFACE_MODE_10GKR] = "10gbase-kr", + [PHY_INTERFACE_MODE_100BASEX] = "100base-x", + [PHY_INTERFACE_MODE_QUSGMII] = "qusgmii", +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) + /* LX2160A SERDES modes */ [PHY_INTERFACE_MODE_25G_AUI] = "25g-aui", [PHY_INTERFACE_MODE_XLAUI] = "xlaui4", [PHY_INTERFACE_MODE_CAUI2] = "caui2", [PHY_INTERFACE_MODE_CAUI4] = "caui4", +#endif +#if defined(CONFIG_PHY_NCSI) [PHY_INTERFACE_MODE_NCSI] = "NC-SI", - [PHY_INTERFACE_MODE_10GBASER] = "10gbase-r", - [PHY_INTERFACE_MODE_USXGMII] = "usxgmii", +#endif }; /* Backplane modes: -- 2.39.2