From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 09189C761A6 for ; Thu, 30 Mar 2023 12:37:56 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 14BB786074; Thu, 30 Mar 2023 14:36:41 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tinylab.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 5E699856E5; Thu, 30 Mar 2023 06:20:57 +0200 (CEST) Received: from bg4.exmail.qq.com (bg4.exmail.qq.com [43.154.221.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 427F385B19 for ; Thu, 30 Mar 2023 06:20:51 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tinylab.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=bmeng@tinylab.org X-QQ-mid: bizesmtp81t1680150042ti1e2j1l Received: from ubuntu.. ( [111.196.129.125]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 30 Mar 2023 12:20:41 +0800 (CST) X-QQ-SSF: 01200000000000D0E000000A0000000 X-QQ-FEAT: fp7GbACbaw756LB+jyPmW4rm3LD0lj4HCvaQSn1vKbzuABlacRk6oA11Is0dD VxB5tjf6y83X1wS2jsdLroZP4De54TBxSQLDo08Z8Pj0UqwaLVqRU2q10jMb5a3Wk0x9ei7 96pRl1TI+LJlspbQkoQNVaM9p9rqVAeSgs6/jNGCNZ6IGMv45YOzuIImcyJ5suwMs7iDOXU wDGBJVZETdnXETy1hP9Z+lhs2hgh9qeMxdJEAbc6DXnfXMlH8E1YBOV1cXCrC2A+MgJ66yV /vlhZJ7DmtoMv0lzOpChrjdVDhy5VRCuIDXl5I/yOOK3tE/kpx3ARXkuk8LtRuJP7N0Jo2O GtQSfunM2YYIyNgx1SqQWqfOTE0NOBuj0lcKICl X-QQ-GoodBg: 0 X-BIZMAIL-ID: 11615140934973401698 From: Bin Meng To: u-boot@lists.denx.de Cc: Leo , Nikita Shubin , Rick Chen Subject: [PATCH 6/8] riscv: Change to use positive offset to access relocation entries Date: Thu, 30 Mar 2023 12:20:22 +0800 Message-Id: <20230330042024.721710-6-bmeng@tinylab.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230330042024.721710-1-bmeng@tinylab.org> References: <20230330042024.721710-1-bmeng@tinylab.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:tinylab.org:qybglogicsvr:qybglogicsvr3 X-Mailman-Approved-At: Thu, 30 Mar 2023 14:36:20 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The codes currently skip the very first relocation entry, and have an inaccurate comment "skip first reserved entry" indicating that the first entry is reserved, but later it references the elements in the first relocation entry using a minus offset. Change to use a positive offset so that there is no need to skip the first relocation entry. Signed-off-by: Bin Meng --- arch/riscv/cpu/start.S | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 879bdc1803..c09d1cb412 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -302,17 +302,12 @@ fix_rela_dyn: add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */ add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */ -/* - * skip first reserved entry: address, type, addend - */ - j 10f - 6: - LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ + LREG t5, REGBYTES(t1) /* t5 <-- relocation info:type */ li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */ bne t5, t3, 8f /* skip non-RISCV_RELOC entries */ - LREG t3, -(REGBYTES*3)(t1) - LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */ + LREG t3, 0(t1) + LREG t5, (REGBYTES * 2)(t1) /* t5 <-- addend */ add t5, t5, t6 /* t5 <-- location to fix up in RAM */ add t3, t3, t6 /* t3 <-- location to fix up in RAM */ SREG t5, 0(t3) @@ -328,19 +323,19 @@ fix_rela_dyn: li t3, RELOC_TYPE bne t5, t3, 10f /* skip non-addned entries */ - LREG t3, -(REGBYTES*3)(t1) + LREG t3, 0(t1) li t5, SYM_SIZE mul t0, t0, t5 add s5, t4, t0 - LREG t0, -(REGBYTES)(t1) /* t0 <-- addend */ + LREG t0, (REGBYTES * 2)(t1) /* t0 <-- addend */ LREG t5, REGBYTES(s5) add t5, t5, t0 add t5, t5, t6 /* t5 <-- location to fix up in RAM */ add t3, t3, t6 /* t3 <-- location to fix up in RAM */ SREG t5, 0(t3) 10: - addi t1, t1, (REGBYTES*3) - ble t1, t2, 6b + addi t1, t1, (REGBYTES * 3) + blt t1, t2, 6b /* * trap update -- 2.34.1