From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 431ECC7618E for ; Sat, 22 Apr 2023 23:56:14 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5182386005; Sun, 23 Apr 2023 01:56:12 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=mailbox.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; secure) header.d=mailbox.org header.i=@mailbox.org header.b="o+X+PJQI"; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="ngk3+ywO"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 08B9786006; Sun, 23 Apr 2023 01:56:11 +0200 (CEST) Received: from mout-p-101.mailbox.org (mout-p-101.mailbox.org [80.241.56.151]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8B1C885FA8 for ; Sun, 23 Apr 2023 01:56:06 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=mailbox.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=marek.vasut+renesas@mailbox.org Received: from smtp1.mailbox.org (smtp1.mailbox.org [IPv6:2001:67c:2050:b231:465::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-101.mailbox.org (Postfix) with ESMTPS id 4Q3pFL24Zqz9sTH; Sun, 23 Apr 2023 01:56:06 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1682207766; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=edch6BVgkRbeZXQ6extlxVJevGr5tw8YTTlrLPz5k0U=; b=o+X+PJQIXhW2d+KOJtbXeYuuHMtfcKubCknYGpRAuxH0MxDQQ0j/eVlusdSYEc8hRclu9F Z/FDdDQau2yKs8h/pBTUQJU+88AJwptyr7mKSO0kIaeb/l9BBJx9qwp21yjb34bWPKh3r6 IkTS6HjoAcNr+/UV6B8sdRm6SqjJczXaJPHqa3WWykyWNnCyUF462HuPbDVdFDVT/zjmzm NidCfLPw9AUWYTc1Y+40RVy+2geWzKWiJdTDjsv9ArodCiOTGr55oi8Rxe6phZGQz41sig synUjFibmTZDpvZmWMnxwfkVvW+Du9oj+gRRLyBNuMUEEL/mBr4XfGJvxBtv+g== From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1682207764; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=edch6BVgkRbeZXQ6extlxVJevGr5tw8YTTlrLPz5k0U=; b=ngk3+ywORviabQGSWieocoyXjz09sPilDDq5ccqLHwXMnxP+o+3Y4lTu9CSo6qzLgPH31L sd4HXuxLK7nGNb0jlMC224XV5GrPC8TEkXHqJ7ghI678iYvRgG8OzH+h2Y4HcTY7iW2X2y FiScsDnwURwPGCkxvZjje4NRqAEo7I2RfsshZ3RntQOUmNw2P7GnAsYxQwvwEJdN6GL+fV 2YNFlIKXDt8iXZGPC1Eg06sWlbgf/ZxvrrpHjo2Y0iJaoN/EcOhIbsLg/5AQF21ADRdesL ol8onA2d9rZcvZ7hOY3b0eLB1nUT+J3XB4bNIM1IeyJhCEx1iWX6XtIZuoYW0A== To: u-boot@lists.denx.de Cc: Takahiro Kuwano , Marek Vasut , Hai Pham , Cong Dang , Jagan Teki , Vignesh R Subject: [PATCH] mtd: spi-nor-core: Add fixups for s25fs512s Date: Sun, 23 Apr 2023 01:55:49 +0200 Message-Id: <20230422235549.92910-1-marek.vasut+renesas@mailbox.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-MBO-RS-ID: ba69089c1cd1411911a X-MBO-RS-META: x7u13ikexwmsigi19iycfyh1bjwa539j X-Rspamd-Queue-Id: 4Q3pFL24Zqz9sTH X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Takahiro Kuwano This patch adds fixups for s25fs512s to address the following issues from reading SFDP: - Non-uniform sectors by factory default. The setting needs to be checked and assign erase hook as needed. - Page size is wrongly advertised in SFDP. - READ_1_1_2 (3Bh/3Ch), READ_1_1_4 (6Bh/6Ch), and PP_1_1_4 (32h/34h) are not supported. - Bank Address Register (BAR) is not supported. In addition, volatile version of Quad Enable is used for safety. Based on patch by Takahiro Kuwano with s25fs_s_post_bfpt_fixup() updated to use 4-byte address commands instead of extended address mode and the page_size is fixed to 256 For future use, manufacturer code should be moved out from framework code as same as in Linux. Reviewed-by: Marek Vasut Signed-off-by: Takahiro Kuwano Signed-off-by: Hai Pham Signed-off-by: Cong Dang Signed-off-by: Marek Vasut --- Cc: Jagan Teki Cc: Takahiro Kuwano Cc: Vignesh R --- drivers/mtd/spi/spi-nor-core.c | 85 ++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 2c3116ee530..a107f71df80 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3199,6 +3199,87 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, /* Use ID byte 4 to distinguish S25FS256T and S25Hx-T */ #define S25FS256T_ID4 (0x08) +/* Number of dummy cycle for Read Any Register (RDAR) op. */ +#define S25FS_S_RDAR_DUMMY 8 + +static int s25fs_s_quad_enable(struct spi_nor *nor) +{ + return spansion_quad_enable_volatile(nor, 0, S25FS_S_RDAR_DUMMY); +} + +static int s25fs_s_erase_non_uniform(struct spi_nor *nor, loff_t addr) +{ + /* Support 8 x 4KB sectors at bottom */ + return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0, SZ_32K); +} + +static int s25fs_s_setup(struct spi_nor *nor, const struct flash_info *info, + const struct spi_nor_flash_parameter *params) +{ + int ret; + u8 cfr3v; + + /* Bank Address Register is not supported */ + if (CONFIG_IS_ENABLED(SPI_FLASH_BAR)) + return -EOPNOTSUPP; + + /* + * Read CR3V to check if uniform sector is selected. If not, assign an + * erase hook that supports non-uniform erase. + */ + ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V, + S25FS_S_RDAR_DUMMY, &cfr3v); + if (ret) + return ret; + if (!(cfr3v & CFR3V_UNHYSA)) + nor->erase = s25fs_s_erase_non_uniform; + + return spi_nor_default_setup(nor, info, params); +} + +static void s25fs_s_default_init(struct spi_nor *nor) +{ + nor->setup = s25fs_s_setup; +} + +static int s25fs_s_post_bfpt_fixup(struct spi_nor *nor, + const struct sfdp_parameter_header *header, + const struct sfdp_bfpt *bfpt, + struct spi_nor_flash_parameter *params) +{ + /* The erase size is set to 4K from BFPT, but it's wrong. Fix it. */ + nor->erase_opcode = SPINOR_OP_SE; + nor->mtd.erasesize = nor->info->sector_size; + + /* The S25FS-S chip family reports 512-byte pages in BFPT but + * in reality the write buffer still wraps at the safe default + * of 256 bytes. Overwrite the page size advertised by BFPT + * to get the writes working. + */ + params->page_size = 256; + + return 0; +} + +static void s25fs_s_post_sfdp_fixup(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) +{ + /* READ_1_1_2 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2; + /* READ_1_1_4 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4; + /* PP_1_1_4 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; + /* Use volatile register to enable quad */ + params->quad_enable = s25fs_s_quad_enable; +} + +static struct spi_nor_fixups s25fs_s_fixups = { + .default_init = s25fs_s_default_init, + .post_bfpt = s25fs_s_post_bfpt_fixup, + .post_sfdp = s25fs_s_post_sfdp_fixup, +}; + static int s25_mdp_ready(struct spi_nor *nor) { u32 addr; @@ -3897,6 +3978,10 @@ void spi_nor_set_fixups(struct spi_nor *nor) if (CONFIG_IS_ENABLED(SPI_FLASH_BAR) && !strcmp(nor->info->name, "s25fl256l")) nor->fixups = &s25fl256l_fixups; + + /* For FS-S (family ID = 0x81) */ + if (JEDEC_MFR(nor->info) == SNOR_MFR_SPANSION && nor->info->id[5] == 0x81) + nor->fixups = &s25fs_s_fixups; #endif #ifdef CONFIG_SPI_FLASH_MT35XU -- 2.39.2