* [PATCH v1 3/3] rockchip: rk3568: add arch_cpu_init()
@ 2021-10-08 2:21 ` Nico Cheng
2021-10-08 17:33 ` Philipp Tomsich
2021-10-09 15:20 ` Kever Yang
0 siblings, 2 replies; 5+ messages in thread
From: Nico Cheng @ 2021-10-08 2:21 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: yamada.masahiro, chenjh, jason.zhu, trini, yifeng.zhao, u-boot,
Nico Cheng
We configured the drive strength and security of EMMC in
arch_cpu_init().
Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com>
---
arch/arm/mach-rockchip/rk3568/rk3568.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
index 973b4f9dcb..3f9a435c3c 100644
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -13,6 +13,14 @@
#define PMUGRF_BASE 0xfdc20000
#define GRF_BASE 0xfdc60000
+#define GRF_GPIO1B_DS_2 0x218
+#define GRF_GPIO1B_DS_3 0x21c
+#define GRF_GPIO1C_DS_0 0x220
+#define GRF_GPIO1C_DS_1 0x224
+#define GRF_GPIO1C_DS_2 0x228
+#define GRF_GPIO1C_DS_3 0x22c
+#define SGRF_BASE 0xFDD18000
+#define SGRF_SOC_CON4 0x10
/* PMU_GRF_GPIO0D_IOMUX_L */
enum {
@@ -81,5 +89,16 @@ void board_debug_uart_init(void)
int arch_cpu_init(void)
{
+#ifdef CONFIG_SPL_BUILD
+ /* Set the emmc sdmmc0 to secure */
+ writel(((0x3 << 11 | 0x1 << 4) << 16), SGRF_BASE + SGRF_SOC_CON4);
+ /* set the emmc ds to level 2 */
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
+#endif
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v1 3/3] rockchip: rk3568: add arch_cpu_init()
2021-10-08 2:21 ` [PATCH v1 3/3] rockchip: rk3568: add arch_cpu_init() Nico Cheng
@ 2021-10-08 17:33 ` Philipp Tomsich
2021-10-09 15:24 ` Kever Yang
2021-10-09 15:20 ` Kever Yang
1 sibling, 1 reply; 5+ messages in thread
From: Philipp Tomsich @ 2021-10-08 17:33 UTC (permalink / raw)
To: Nico Cheng
Cc: Simon Glass, Kever Yang, yamada.masahiro, chenjh, jason.zhu,
trini, Yifeng Zhao, U-Boot Mailing List
On Fri, 8 Oct 2021 at 04:01, Nico Cheng <nico.cheng@rock-chips.com> wrote:
>
> We configured the drive strength and security of EMMC in
> arch_cpu_init().
Could you point me to a public version of the TRM (and
ideally also of the datasheet), so I can review this series?
Thanks,
Philipp.
>
> Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com>
> ---
>
> arch/arm/mach-rockchip/rk3568/rk3568.c | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
> index 973b4f9dcb..3f9a435c3c 100644
> --- a/arch/arm/mach-rockchip/rk3568/rk3568.c
> +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
> @@ -13,6 +13,14 @@
>
> #define PMUGRF_BASE 0xfdc20000
> #define GRF_BASE 0xfdc60000
> +#define GRF_GPIO1B_DS_2 0x218
> +#define GRF_GPIO1B_DS_3 0x21c
> +#define GRF_GPIO1C_DS_0 0x220
> +#define GRF_GPIO1C_DS_1 0x224
> +#define GRF_GPIO1C_DS_2 0x228
> +#define GRF_GPIO1C_DS_3 0x22c
> +#define SGRF_BASE 0xFDD18000
> +#define SGRF_SOC_CON4 0x10
>
> /* PMU_GRF_GPIO0D_IOMUX_L */
> enum {
> @@ -81,5 +89,16 @@ void board_debug_uart_init(void)
>
> int arch_cpu_init(void)
> {
> +#ifdef CONFIG_SPL_BUILD
> + /* Set the emmc sdmmc0 to secure */
> + writel(((0x3 << 11 | 0x1 << 4) << 16), SGRF_BASE + SGRF_SOC_CON4);
> + /* set the emmc ds to level 2 */
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
> +#endif
> return 0;
> }
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v1 3/3] rockchip: rk3568: add arch_cpu_init()
2021-10-08 2:21 ` [PATCH v1 3/3] rockchip: rk3568: add arch_cpu_init() Nico Cheng
2021-10-08 17:33 ` Philipp Tomsich
@ 2021-10-09 15:20 ` Kever Yang
1 sibling, 0 replies; 5+ messages in thread
From: Kever Yang @ 2021-10-09 15:20 UTC (permalink / raw)
To: Nico Cheng, sjg, philipp.tomsich
Cc: yamada.masahiro, chenjh, jason.zhu, trini, yifeng.zhao, u-boot
On 2021/10/8 上午10:21, Nico Cheng wrote:
> We configured the drive strength and security of EMMC in
typo: drive/driver.
EMMC and sdmmc
> arch_cpu_init().
>
> Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com>
> ---
>
> arch/arm/mach-rockchip/rk3568/rk3568.c | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
> index 973b4f9dcb..3f9a435c3c 100644
> --- a/arch/arm/mach-rockchip/rk3568/rk3568.c
> +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
> @@ -13,6 +13,14 @@
>
> #define PMUGRF_BASE 0xfdc20000
> #define GRF_BASE 0xfdc60000
> +#define GRF_GPIO1B_DS_2 0x218
> +#define GRF_GPIO1B_DS_3 0x21c
> +#define GRF_GPIO1C_DS_0 0x220
> +#define GRF_GPIO1C_DS_1 0x224
> +#define GRF_GPIO1C_DS_2 0x228
> +#define GRF_GPIO1C_DS_3 0x22c
> +#define SGRF_BASE 0xFDD18000
> +#define SGRF_SOC_CON4 0x10
>
> /* PMU_GRF_GPIO0D_IOMUX_L */
> enum {
> @@ -81,5 +89,16 @@ void board_debug_uart_init(void)
>
> int arch_cpu_init(void)
> {
> +#ifdef CONFIG_SPL_BUILD
> + /* Set the emmc sdmmc0 to secure */
> + writel(((0x3 << 11 | 0x1 << 4) << 16), SGRF_BASE + SGRF_SOC_CON4);
Please use rk_clrreg to clr the reg.
> + /* set the emmc ds to level 2 */
Please use driver strength instead of 'ds'.
Thanks,
- Kever
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
> +#endif
> return 0;
> }
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v1 3/3] rockchip: rk3568: add arch_cpu_init()
2021-10-08 17:33 ` Philipp Tomsich
@ 2021-10-09 15:24 ` Kever Yang
2021-10-31 14:56 ` Alper Nebi Yasak
0 siblings, 1 reply; 5+ messages in thread
From: Kever Yang @ 2021-10-09 15:24 UTC (permalink / raw)
To: Philipp Tomsich, Nico Cheng
Cc: Simon Glass, yamada.masahiro, chenjh, jason.zhu, trini,
Yifeng Zhao, U-Boot Mailing List
Hi Philipp,
On 2021/10/9 上午1:33, Philipp Tomsich wrote:
> On Fri, 8 Oct 2021 at 04:01, Nico Cheng <nico.cheng@rock-chips.com> wrote:
>> We configured the drive strength and security of EMMC in
>> arch_cpu_init().
> Could you point me to a public version of the TRM (and
> ideally also of the datasheet), so I can review this series?
I believe there is no public TRM or datasheet for rk3568 is available
for now.
For these setting, I believe they are ported from vendor tree with
enough test, but clear enough
comments will be needed.
Thanks,
- Kever
>
> Thanks,
> Philipp.
>
>> Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com>
>> ---
>>
>> arch/arm/mach-rockchip/rk3568/rk3568.c | 19 +++++++++++++++++++
>> 1 file changed, 19 insertions(+)
>>
>> diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
>> index 973b4f9dcb..3f9a435c3c 100644
>> --- a/arch/arm/mach-rockchip/rk3568/rk3568.c
>> +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
>> @@ -13,6 +13,14 @@
>>
>> #define PMUGRF_BASE 0xfdc20000
>> #define GRF_BASE 0xfdc60000
>> +#define GRF_GPIO1B_DS_2 0x218
>> +#define GRF_GPIO1B_DS_3 0x21c
>> +#define GRF_GPIO1C_DS_0 0x220
>> +#define GRF_GPIO1C_DS_1 0x224
>> +#define GRF_GPIO1C_DS_2 0x228
>> +#define GRF_GPIO1C_DS_3 0x22c
>> +#define SGRF_BASE 0xFDD18000
>> +#define SGRF_SOC_CON4 0x10
>>
>> /* PMU_GRF_GPIO0D_IOMUX_L */
>> enum {
>> @@ -81,5 +89,16 @@ void board_debug_uart_init(void)
>>
>> int arch_cpu_init(void)
>> {
>> +#ifdef CONFIG_SPL_BUILD
>> + /* Set the emmc sdmmc0 to secure */
>> + writel(((0x3 << 11 | 0x1 << 4) << 16), SGRF_BASE + SGRF_SOC_CON4);
>> + /* set the emmc ds to level 2 */
>> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
>> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
>> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
>> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
>> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
>> + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
>> +#endif
>> return 0;
>> }
>> --
>> 2.17.1
>>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v1 3/3] rockchip: rk3568: add arch_cpu_init()
2021-10-09 15:24 ` Kever Yang
@ 2021-10-31 14:56 ` Alper Nebi Yasak
0 siblings, 0 replies; 5+ messages in thread
From: Alper Nebi Yasak @ 2021-10-31 14:56 UTC (permalink / raw)
To: Kever Yang, Philipp Tomsich, Nico Cheng
Cc: Simon Glass, yamada.masahiro, chenjh, jason.zhu, trini,
Yifeng Zhao, U-Boot Mailing List
On 09/10/2021 18:24, Kever Yang wrote:
> On 2021/10/9 上午1:33, Philipp Tomsich wrote:
>> Could you point me to a public version of the TRM (and
>> ideally also of the datasheet), so I can review this series?
>
> I believe there is no public TRM or datasheet for rk3568 is available
> for now.
I see both TRM and datasheet on T-Firefly's website [1]. Both are
watermarked "Rockchip Confidential", are these OK to use despite that?
[1] https://www.t-firefly.com/doc/download/107.html#other_437
(English version of the site appears to be hijacked
and replaced with a fake version)
^ permalink raw reply [flat|nested] 5+ messages in thread
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2021-10-08 2:21 ` [PATCH v1 3/3] rockchip: rk3568: add arch_cpu_init() Nico Cheng
2021-10-08 17:33 ` Philipp Tomsich
2021-10-09 15:24 ` Kever Yang
2021-10-31 14:56 ` Alper Nebi Yasak
2021-10-09 15:20 ` Kever Yang
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