From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 017FFC433F5 for ; Sat, 9 Oct 2021 15:04:54 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C69E060F6C for ; Sat, 9 Oct 2021 15:04:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C69E060F6C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 23B5283616; Sat, 9 Oct 2021 17:04:50 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id DCA338364A; Sat, 9 Oct 2021 17:04:48 +0200 (CEST) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.70.206]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7911182C7D for ; Sat, 9 Oct 2021 17:04:43 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=kever.yang@rock-chips.com Received: from localhost (unknown [192.168.167.70]) by regular1.263xmail.com (Postfix) with ESMTP id EA3B61AC2 for ; Sat, 9 Oct 2021 23:04:38 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-SKE-CHECKED: 1 X-ABS-CHECKED: 1 X-ANTISPAM-LEVEL: 2 Received: from [192.168.0.110] (unknown [112.49.233.219]) by smtp.263.net (postfix) whith ESMTP id P20679T139864623802112S1633791876584516_; Sat, 09 Oct 2021 23:04:37 +0800 (CST) X-IP-DOMAINF: 1 X-RL-SENDER: kever.yang@rock-chips.com X-SENDER: yk@rock-chips.com X-LOGIN-NAME: kever.yang@rock-chips.com X-FST-TO: sjg@chromium.org X-RCPT-COUNT: 5 X-LOCAL-RCPT-COUNT: 1 X-SENDER-IP: 112.49.233.219 X-ATTACHMENT-NUM: 0 X-UNIQUE-TAG: <6ff31d5e4bccb591f0ec028827a13b0b> X-System-Flag: 0 Subject: Re: [PATCH v3 1/2] spi: rockchip_sfc: Implement set_speed logic To: Jon Lin , jagan@amarulasolutions.com Cc: u-boot@lists.denx.de, macromorgan@hotmail.com, sjg@chromium.org References: <20210917211424.v3.1.I2ce354b421327523e663c63063c3393415ff3dae@changeid> From: Kever Yang Message-ID: <980a0fbd-5813-1681-9cff-58b9214802a7@rock-chips.com> Date: Sat, 9 Oct 2021 23:04:37 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20210917211424.v3.1.I2ce354b421327523e663c63063c3393415ff3dae@changeid> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On 2021/9/17 下午9:14, Jon Lin wrote: > Set clock related processing into set_speed logic. And Optimize > printing format. > > Tested-by: Chris Morgan > Signed-off-by: Jon Lin Reviewed-by: Kever Yang Thanks, - Kever > --- > > Changes in v3: > - Remove useless headfile > - Fix misspelling > > drivers/spi/rockchip_sfc.c | 82 ++++++++++++++++++-------------------- > 1 file changed, 39 insertions(+), 43 deletions(-) > > diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c > index 4e2b861f22..94222df5ce 100644 > --- a/drivers/spi/rockchip_sfc.c > +++ b/drivers/spi/rockchip_sfc.c > @@ -116,6 +116,7 @@ > > /* Master trigger */ > #define SFC_DMA_TRIGGER 0x80 > +#define SFC_DMA_TRIGGER_START 1 > > /* Src or Dst addr for master */ > #define SFC_DMA_ADDR 0x84 > @@ -163,14 +164,12 @@ > #define SFC_DMA_TRANS_THRETHOLD (0x40) > > /* Maximum clock values from datasheet suggest keeping clock value under > - * 150MHz. No minimum or average value is suggested, but the U-boot BSP driver > - * has a minimum of 10MHz and a default of 80MHz which seems reasonable. > + * 150MHz. No minimum or average value is suggested. > */ > -#define SFC_MIN_SPEED_HZ (10 * 1000 * 1000) > -#define SFC_DEFAULT_SPEED_HZ (80 * 1000 * 1000) > -#define SFC_MAX_SPEED_HZ (150 * 1000 * 1000) > +#define SFC_MAX_SPEED (150 * 1000 * 1000) > > struct rockchip_sfc { > + struct udevice *dev; > void __iomem *regbase; > struct clk hclk; > struct clk clk; > @@ -197,8 +196,6 @@ static int rockchip_sfc_reset(struct rockchip_sfc *sfc) > /* Still need to clear the masked interrupt from RISR */ > writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); > > - debug("reset\n"); > - > return err; > } > > @@ -261,15 +258,11 @@ static int rockchip_sfc_probe(struct udevice *bus) > #if CONFIG_IS_ENABLED(CLK) > ret = clk_enable(&sfc->hclk); > if (ret) > - debug("Enable ahb clock fail %s: %d\n", bus->name, ret); > + dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n", bus->name, ret); > > ret = clk_enable(&sfc->clk); > if (ret) > - debug("Enable clock fail for %s: %d\n", bus->name, ret); > - > - ret = clk_set_rate(&sfc->clk, SFC_DEFAULT_SPEED_HZ); > - if (ret) > - debug("Could not set sfc clock for %s: %d\n", bus->name, ret); > + dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n", bus->name, ret); > #endif > > ret = rockchip_sfc_init(sfc); > @@ -278,7 +271,8 @@ static int rockchip_sfc_probe(struct udevice *bus) > > sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc); > sfc->version = rockchip_sfc_get_version(sfc); > - sfc->speed = SFC_DEFAULT_SPEED_HZ; > + sfc->max_freq = SFC_MAX_SPEED; > + sfc->dev = bus; > > return 0; > > @@ -411,11 +405,11 @@ static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, > ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE; > cmd |= plat->cs << SFC_CMD_CS_SHIFT; > > - debug("addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", > - op->addr.nbytes, op->addr.buswidth, > - op->dummy.nbytes, op->dummy.buswidth); > - debug("ctrl=%x cmd=%x addr=%llx len=%x\n", > - ctrl, cmd, op->addr.val, len); > + dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", > + op->addr.nbytes, op->addr.buswidth, > + op->dummy.nbytes, op->dummy.buswidth); > + dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n", > + ctrl, cmd, op->addr.val, len); > > writel(ctrl, sfc->regbase + SFC_CTRL); > writel(cmd, sfc->regbase + SFC_CMD); > @@ -492,7 +486,7 @@ static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t d > { > writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); > writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR); > - writel(0x1, sfc->regbase + SFC_DMA_TRIGGER); > + writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER); > > return len; > } > @@ -500,7 +494,7 @@ static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t d > static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc, > const struct spi_mem_op *op, u32 len) > { > - debug("xfer_poll len=%x\n", len); > + dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len); > > if (op->data.dir == SPI_MEM_DATA_OUT) > return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len); > @@ -516,7 +510,7 @@ static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, > void *dma_buf; > int ret; > > - debug("xfer_dma len=%x\n", len); > + dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len); > > if (op->data.dir == SPI_MEM_DATA_OUT) { > dma_buf = (void *)op->data.buf.out; > @@ -564,33 +558,16 @@ static int rockchip_sfc_exec_op(struct spi_slave *mem, > u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); > int ret; > > -#if CONFIG_IS_ENABLED(CLK) > - if (unlikely(mem->max_hz != sfc->speed)) { > - ret = clk_set_rate(&sfc->clk, clamp(mem->max_hz, (uint)SFC_MIN_SPEED_HZ, > - (uint)SFC_MAX_SPEED_HZ)); > - if (ret < 0) { > - printf("set_freq=%dHz fail, check if it's the cru support level\n", > - mem->max_hz); > - return ret; > - } > - > - sfc->max_freq = mem->max_hz; > - sfc->speed = mem->max_hz; > - debug("set_freq=%dHz real_freq=%dHz\n", sfc->max_freq, sfc->speed); > - } > -#endif > - > rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); > - > rockchip_sfc_xfer_setup(sfc, mem, op, len); > if (len) { > - if (likely(sfc->use_dma) && !(len & 0x3) && len >= SFC_DMA_TRANS_THRETHOLD) > + if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD) > ret = rockchip_sfc_xfer_data_dma(sfc, op, len); > else > ret = rockchip_sfc_xfer_data_poll(sfc, op, len); > > if (ret != len) { > - printf("xfer data failed ret %d dir %d\n", ret, op->data.dir); > + dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir); > > return -EIO; > } > @@ -604,13 +581,32 @@ static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op > struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent); > > op->data.nbytes = min(op->data.nbytes, sfc->max_iosize); > + > return 0; > } > > static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) > { > - /* We set up speed later for each transmission. > - */ > + struct rockchip_sfc *sfc = dev_get_plat(bus); > + > + if (speed > sfc->max_freq) > + speed = sfc->max_freq; > + > + if (speed == sfc->speed) > + return 0; > + > +#if CONFIG_IS_ENABLED(CLK) > + int ret = clk_set_rate(&sfc->clk, speed); > + > + if (ret < 0) { > + dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n", > + speed); > + return ret; > + } > + sfc->speed = speed; > +#else > + dev_dbg(sfc->dev, "sfc failed, CLK not support\n"); > +#endif > return 0; > } >