From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4EECBC433EF for ; Thu, 24 Mar 2022 08:28:55 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2FC158406B; Thu, 24 Mar 2022 09:28:52 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="JmGiG+6b"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A144584062; Thu, 24 Mar 2022 09:28:50 +0100 (CET) Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 42C3A8406C for ; Thu, 24 Mar 2022 09:28:46 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=heiko.thiery@gmail.com Received: by mail-wr1-x436.google.com with SMTP id r13so5473615wrr.9 for ; Thu, 24 Mar 2022 01:28:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=b0Tt/pR/dSXbXdI6tYFoPqoo+3fgGp+FYL/n46ZJPGk=; b=JmGiG+6bXwFOfaxGFieWdDZjB9fHglxN1j4dMd96TMjygtElHlmM9iZC18m+hj/+hL iuuKRvbbjHLy9z/ctlbsiNUeb2O2LZThASZxm4enzz87+rY4gVJ/cctNuto63wbiS3Cj /0bkF1QWYYbqCdEygj11OOm5W4i82bOmLFc7nrg8pbKf4ppwFQ0m8WH6mEVxDW3kBzV7 kX1jO+aQt0MethXa7XYfv24pBBpBt+eLpI3hLxJ994vOW6FzfsSFFffSN1boGwHO4kKX NvDdPOiI1efFrofkMybMIGQ5j+5B4KEpNESafPEsydrPU7jRlWfrQTvEyOMZjNztWXTa 1jRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=b0Tt/pR/dSXbXdI6tYFoPqoo+3fgGp+FYL/n46ZJPGk=; b=eX0mVC10G1JEtAaoFxijOjkqcA2crVoKz2fd0deb/B0RvIej910tdB7hdnUsdoa6Tk KXWft/TfjsqZLmyKpzt5fXEwxYqIBClQczDuWMOXXybGj3iFWAqpdHoZIBwZn37aiBQX uDMEJ7Wl1Gy5Jdat/3pVzhPGc2gkV7RkEN/qlyVo/QloHPDa1G+H/wNDb41+CwmMOolI Btv9Iptw3wGHzWWRx3e+5XEdFDKUKDvMgSAc0JSSXQ9hjvHjouDHohFgsbEqwJ59tz9N DCIB8S17TCftb5bVlNQCwVx9XyJq7AMs7L7VphVyRDOkQe6elS7i5USe5+jfoGs1dP4U Rang== X-Gm-Message-State: AOAM53225pDDEvbfv49BFx/C16RbUeb1vFXLewtRO3lenEEDOTcezg04 aDprCGz7n21EsV20MLftPMjOAeaJQrBCEmq9rUI= X-Google-Smtp-Source: ABdhPJz+6FKK1SdFzt0VZH35HLNOp8os6ITynd8Sw5YjfWzAotYjnvy7Yg75Zy6yvQgqlk+sF8LCOXYMGf77L3lsAzg= X-Received: by 2002:a05:6000:10ca:b0:205:9b86:7976 with SMTP id b10-20020a05600010ca00b002059b867976mr282916wrx.542.1648110525667; Thu, 24 Mar 2022 01:28:45 -0700 (PDT) MIME-Version: 1.0 References: <20220315130820.1054186-1-angus@akkea.ca> <20220315130820.1054186-3-angus@akkea.ca> In-Reply-To: <20220315130820.1054186-3-angus@akkea.ca> From: Heiko Thiery Date: Thu, 24 Mar 2022 09:28:34 +0100 Message-ID: Subject: Re: [PATCH v4 2/4] clk: imx8mq: Add a clock driver for the imx8mq To: Angus Ainslie Cc: u-boot@lists.denx.de, Marek Vasut , lukma@denx.de, seanga2@gmail.com, sbabic@denx.de, festevam@gmail.com, kernel@puri.sm, uboot-imx@nxp.com, peng.fan@nxp.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Hi Angus, could you include the UART clocks? Am Di., 15. M=C3=A4rz 2022 um 14:09 Uhr schrieb Angus Ainslie : > > This is a DM clock driver based off the imx8mm u-boot driver and the linu= x > kernel driver. > > All of the PLLs and clocks are initialized so the subsystems below are > functional and tested. > > 1) USB host and peripheral > 2) ECSPI > 3) UART > 4) I2C all busses > 5) USDHC for eMMC support > 6) USB storage > 7) GPIO > 8) DRAM > > Signed-off-by: Angus Ainslie > --- Could you include the UART clocks? Or should I wait until your patch is accepted and then send this one after? diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index c3b685dbaa..b2d92f4776 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -82,6 +82,23 @@ static const char *imx8mq_i2c4_sels[] =3D {"clock-osc-25m", "sys_pll1_160m", "sys_ "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m",= }; +static const char * const imx8mq_uart1_sels[] =3D {"clock-osc-25m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; + +static const char * const imx8mq_uart2_sels[] =3D {"clock-osc-25m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + +static const char * const imx8mq_uart3_sels[] =3D {"clock-osc-25m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; + +static const char * const imx8mq_uart4_sels[] =3D {"clock-osc-25m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + + static const char *imx8mq_wdog_sels[] =3D {"clock-osc-25m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }= ; @@ -358,6 +375,16 @@ static int imx8mq_clk_probe(struct udevice *dev) imx8m_clk_composite("i2c3", imx8mq_i2c3_sels, base + 0xae00)= ); clk_dm(IMX8MQ_CLK_I2C4, imx8m_clk_composite("i2c4", imx8mq_i2c4_sels, base + 0xae80)= ); + + clk_dm(IMX8MQ_CLK_UART1, + imx8m_clk_composite("uart1", imx8mq_uart1_sels, base + 0xaf0= 0)); + clk_dm(IMX8MQ_CLK_UART2, + imx8m_clk_composite("uart2", imx8mq_uart2_sels, base + 0xaf8= 0)); + clk_dm(IMX8MQ_CLK_UART3, + imx8m_clk_composite("uart3", imx8mq_uart3_sels, base + 0xb00= 0)); + clk_dm(IMX8MQ_CLK_UART4, + imx8m_clk_composite("uart4", imx8mq_uart4_sels, base + 0xb08= 0)); + clk_dm(IMX8MQ_CLK_WDOG, imx8m_clk_composite("wdog", imx8mq_wdog_sels, base + 0xb900)= ); clk_dm(IMX8MQ_CLK_QSPI, @@ -387,6 +414,16 @@ static int imx8mq_clk_probe(struct udevice *dev) imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0)); clk_dm(IMX8MQ_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0)); + + clk_dm(IMX8MQ_CLK_UART1_ROOT, + imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0)); + clk_dm(IMX8MQ_CLK_UART2_ROOT, + imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); + clk_dm(IMX8MQ_CLK_UART3_ROOT, + imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); + clk_dm(IMX8MQ_CLK_UART4_ROOT, + imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0)); + clk_dm(IMX8MQ_CLK_OCOTP_ROOT, imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0= )); clk_dm(IMX8MQ_CLK_USDHC1_ROOT, [SNIP] --=20 Heiko