From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 603BEC19F2D for ; Tue, 9 Aug 2022 13:25:31 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 947D884A34; Tue, 9 Aug 2022 15:25:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="NzBQ8wUC"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 861D784A45; Tue, 9 Aug 2022 15:25:25 +0200 (CEST) Received: from mail-yb1-xb31.google.com (mail-yb1-xb31.google.com [IPv6:2607:f8b0:4864:20::b31]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 36BB9841E0 for ; Tue, 9 Aug 2022 15:25:22 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-yb1-xb31.google.com with SMTP id 199so18276658ybl.9 for ; Tue, 09 Aug 2022 06:25:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=k6nXavoAGZ7nn07yhkYaNHWoSCCVm2PLvbtc1/Wy0s4=; b=NzBQ8wUC0uyEZTttvaEpkRLqKl+0Wf07zN6CYCqj6CuATEuDE14L0niVPjrOxVAMw/ t4jaLK9dCDgs3YJhj7crV3FXG4jLaauj+Rs1IYDf39hWHGyXgaS8yD5QaDEMTsnhZl9e RT+/Doiu5OIfEv6KexKD4tOd6KjIWMXat1NxTR4I9HMMIGqpvUD8SEf21z8PYIpSMouB 4Vy3bUWLbJaRtgCsURR1r5eXTi9aKaH1C+7ySk2HAHq1kFEbqaHiNIZx0LXq7Zjb1A3O 18Ob3uS9xuDuLJrPLVQuo7J4nOc2YGMvNgM9I7Bo0nJZWzAzS4iS5m63/HSqTzVepU8W RHzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=k6nXavoAGZ7nn07yhkYaNHWoSCCVm2PLvbtc1/Wy0s4=; b=PBMfx99fHGYMax4G9qrC0i4sxNQNRMDBChv3C1Y7nK6jW5kZZFC54DbAVtP1e/TxFr Jx2Ax15eTeGKEA9izZXgqo1e37vT+3hY9L+Dy/1fmXWz6R06fXDXLyiiVD2g40F/mquO dW8RmLblPSbBSCwR6HeGjhZ5yMQE4ZX6DD26SYF1EvnsUlvCnOPU8LPwNm4o3RRBJPTt YdxXqCFBS2lW44WhjMaN+Cy23r4OYZVClxii6tWEn1ubdtY+vZJMiFQTi3KkGuHX4yAF RSaiop08b2/8qx0kjanKHwIgSqJCM692vYkjBuecyCsjBiyHkmwGIkYv8Vnyzb4SeM39 OKgA== X-Gm-Message-State: ACgBeo0U9pMxMiuJ7+Peay+etiD9U2bZb/45octnChnlRsa6w6e2sLfE wKpQIz577OKm5IJ9jBXs6gZwmmXAvGsrHFBVBzSdcQ== X-Google-Smtp-Source: AA6agR6XPy+Emh86EsCHk3lVrkZ5o5XP5sOELD+FnzYdhYP6om0uRILjAhJdBZEMgYTJUyUwVMKsIR78vhHv11phSig= X-Received: by 2002:a25:d013:0:b0:671:8628:9753 with SMTP id h19-20020a25d013000000b0067186289753mr20247074ybg.462.1660051520809; Tue, 09 Aug 2022 06:25:20 -0700 (PDT) MIME-Version: 1.0 References: <20220804142721.536556-1-sumit.garg@linaro.org> <20220804142721.536556-5-sumit.garg@linaro.org> In-Reply-To: From: Sumit Garg Date: Tue, 9 Aug 2022 18:55:09 +0530 Message-ID: Subject: Re: [PATCH 04/13] reset: qcom: Add support for QCS404 SoC reset table To: Robert Marko Cc: u-boot@lists.denx.de, rfried.dev@gmail.com, jorge.ramirez.ortiz@gmail.com, sjg@chromium.org, trini@konsulko.com, stephan@gerhold.net, mario.six@gdsys.cc, dsankouski@gmail.com, luka.kovacic@sartura.hr, luka.perkov@sartura.hr, jh80.chung@samsung.com, nicolas.dechesne@linaro.org, vinod.koul@linaro.org, mworsfold@impinj.com, lgillham@impinj.com, daniel.thompson@linaro.org, pbrobinson@gmail.com Content-Type: text/plain; charset="UTF-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Hi Robert, Thanks for your review. On Sat, 6 Aug 2022 at 13:11, Robert Marko wrote: > > On Thu, Aug 4, 2022 at 4:28 PM Sumit Garg wrote: > > > > Signed-off-by: Sumit Garg > > --- > > drivers/reset/reset-qcom.c | 30 ++++++++++++++++++++++++++++++ > > 1 file changed, 30 insertions(+) > > > > diff --git a/drivers/reset/reset-qcom.c b/drivers/reset/reset-qcom.c > > index 40f436ede4..94315e76d5 100644 > > --- a/drivers/reset/reset-qcom.c > > +++ b/drivers/reset/reset-qcom.c > > @@ -102,6 +102,35 @@ static const struct qcom_reset_map gcc_qcom_resets[] = { > > }; > > #endif > > > > +#ifdef CONFIG_TARGET_QCS404EVB > > Hi, > Why not pass the reset maps via match data per compatible? > Yeah but that won't allow me to get rid of this "#ifdef" since bindings header (qcom,gcc-qcs404.h) and corresponding reset table needs to be included under it due to overlapping reset IDs. So it won't add any value. -Sumit > Regards, > Robert > > > +#include > > +static const struct qcom_reset_map gcc_qcom_resets[] = { > > + [GCC_GENI_IR_BCR] = { 0x0F000 }, > > + [GCC_CDSP_RESTART] = { 0x18000 }, > > + [GCC_USB_HS_BCR] = { 0x41000 }, > > + [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 }, > > + [GCC_QUSB2_PHY_BCR] = { 0x4103c }, > > + [GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 }, > > + [GCC_USB2A_PHY_BCR] = { 0x0000c, 0 }, > > + [GCC_USB3_PHY_BCR] = { 0x39004 }, > > + [GCC_USB_30_BCR] = { 0x39000 }, > > + [GCC_USB3PHY_PHY_BCR] = { 0x39008 }, > > + [GCC_PCIE_0_BCR] = { 0x3e000 }, > > + [GCC_PCIE_0_PHY_BCR] = { 0x3e004 }, > > + [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 }, > > + [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c }, > > + [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6}, > > + [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 }, > > + [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 }, > > + [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 }, > > + [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 }, > > + [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 }, > > + [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 }, > > + [GCC_EMAC_BCR] = { 0x4e000 }, > > + [GCC_WDSP_RESTART] = {0x19000}, > > +}; > > +#endif > > + > > static int qcom_reset_assert(struct reset_ctl *rst) > > { > > struct qcom_reset_priv *priv = dev_get_priv(rst->dev); > > @@ -141,6 +170,7 @@ static const struct reset_ops qcom_reset_ops = { > > > > static const struct udevice_id qcom_reset_ids[] = { > > { .compatible = "qcom,gcc-reset-ipq4019" }, > > + { .compatible = "qcom,gcc-reset-qcs404" }, > > { } > > }; > > > > -- > > 2.25.1 > > > > > -- > Robert Marko > Staff Embedded Linux Engineer > Sartura Ltd. > Lendavska ulica 16a > 10000 Zagreb, Croatia > Email: robert.marko@sartura.hr > Web: www.sartura.hr