From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 78BBAC433EF for ; Fri, 15 Jul 2022 09:16:38 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 013F981F69; Fri, 15 Jul 2022 11:16:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="f/MyPc2J"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 766FF8212A; Fri, 15 Jul 2022 11:16:33 +0200 (CEST) Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0FF2A8210C for ; Fri, 15 Jul 2022 11:16:31 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jagan@amarulasolutions.com Received: by mail-ej1-x636.google.com with SMTP id mf4so7937352ejc.3 for ; Fri, 15 Jul 2022 02:16:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=60jti/jkENG3c/r3KNuK61DilQ+CrOOAxQ+1vpb63qg=; b=f/MyPc2JBsj7Uc836uX50mZF/41AhiPKIZvhGAFLrsWsxRyD413lexQ2DZyRvLBPNd DBMvVy/jyC3dai1THeSUasmFE6gl7MDqQY88L1rtx0unDJPrOz+SEn6wlkFypZ3pwP+c W4P7Ss+yPZ+GJGynMuOW5Q6fJ+KY4mHaeBFzQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=60jti/jkENG3c/r3KNuK61DilQ+CrOOAxQ+1vpb63qg=; b=xlN3acAJ83VnpToRipRUJpfOBx/0HiLdaZLNCTLX+kASamVPlWmGlgf4XojECtVnKV Y2OfO1DYOZlq0b9WQo6rbZjcItXgSAy1uupCEXY1SOOKhRpPizCki/mF9VNNn1JpSsPI oUy2gt8qIQCcEbGnUgizyenqZW/XSNRCqOqZXuFC3m6pQxRj2w9HvEK/YZ7AnEpLTftG IU1tseA0tYvZOj0Q5a5ZIYMH8oORdXBVzyBx3r1t+/SYdLHYH9vDEHT9nPL1zzeyKvU4 30dDny1CxQvIMrvvgt86mEGsCRmelQiuS1u8//t4Xab5OHV+5GodBkOElyqa3epKNxGc lWBw== X-Gm-Message-State: AJIora+F8VtCt1Dmv/w0QPOXEAlaGw5B8pBGWaB5W91XDRjLvQhVa3LB sDqFV2SnJhDuV574JENOeVCG9I5x2CSXyv4uvNwO9KeOM5KzTld1 X-Google-Smtp-Source: AGRyM1vonfs5fq9kegsKBcHTkHT2Sy7R95XvwWepfH9FX48RtFtYQ9UYWjKvNmV5zMaRVpvwjnqPzn8NrJDNdSgpMmo= X-Received: by 2002:a17:907:160f:b0:726:9467:9be8 with SMTP id hb15-20020a170907160f00b0072694679be8mr12683445ejc.770.1657876590633; Fri, 15 Jul 2022 02:16:30 -0700 (PDT) MIME-Version: 1.0 References: <20220715040922.451-1-samuel@sholland.org> <20220715040922.451-4-samuel@sholland.org> In-Reply-To: <20220715040922.451-4-samuel@sholland.org> From: Jagan Teki Date: Fri, 15 Jul 2022 14:46:19 +0530 Message-ID: Subject: Re: [PATCH 3/4] phy: sun4i-usb: Rework HCI PHY (aka "pmu_unk1") handling To: Samuel Holland Cc: u-boot@lists.denx.de, Andre Przywara , Joe Hershberger Content-Type: text/plain; charset="UTF-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Fri, Jul 15, 2022 at 9:39 AM Samuel Holland wrote: > > From: Andre Przywara > > As Icenowy pointed out, newer manuals (starting with H6) actually > document the register block at offset 0x800 as "HCI controller and PHY > interface", also describe the bits in our "PMU_UNK1" register. > Let's put proper names to those "unknown" variables and symbols. > > While we are at it, generalise the existing code by allowing a bitmap > of bits to clear and set, to cover newer SoCs: The A100 and H616 use a > different bit for the SIDDQ control. > > Signed-off-by: Andre Przywara > Signed-off-by: Samuel Holland > --- Reviewed-by: Jagan Teki