From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7580C43334 for ; Fri, 15 Jul 2022 09:24:40 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C7D69807E0; Fri, 15 Jul 2022 11:24:38 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="rpRUXmHV"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id E5D0A808A6; Fri, 15 Jul 2022 11:24:36 +0200 (CEST) Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 344D88036F for ; Fri, 15 Jul 2022 11:24:34 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jagan@amarulasolutions.com Received: by mail-ej1-x633.google.com with SMTP id dn9so7934657ejc.7 for ; Fri, 15 Jul 2022 02:24:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=oZaZek408L4a9oCDAbwjaS4Ysu5PFkHUluXkANK1bJs=; b=rpRUXmHVyeNDPjczDl4CCHs8DBi/6xSHPS66Xbonlrx71ExoNHogl1TQfkhLcf8wAB hQh+VcNm7iPdfFC8x85lR1b1y3bsCbVYSw4pkTQBJ9g5AviLj8anpS5d6Zcb5XfiS3fr Dd5ySoVgPGFDXqTZ3AN+nUo+3qo7CNdJb5dVY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=oZaZek408L4a9oCDAbwjaS4Ysu5PFkHUluXkANK1bJs=; b=14eHcEZjW+ZqxUaBynsqhJajNbSq5/AHCldCuYI40bXReXzr+D+HQOk8SaRvS2C3Rq 3DVrTHcq1/4ySbsHHciA3xnHTb89jdKMM7H4gljtHHO+o6I66bkb4ts2oH1VkzxPho3w taFUinQ+qSKf3nQD78nHvtZL3NILb4ZGSeIDqOoZE8Q51Oa/YO2FmwsU9jnLZEUt3rj8 AYNtzdZbtTme0OyEFcKCLGOl+BltFBnpWgZVjEPCOvHiIg7Ugkx580fmjp0BgJnXCu8x /UjIOj3C6DqWpLg1yw3A9jCo+Q9r89eJUq36Kvz2Upclxa74OUgHcewJ9W8fT2Kecpbw 7kOg== X-Gm-Message-State: AJIora9RZiEWXtpHLlEUTM8ZUwfZDswKrqtOjgitiVDD1oI+lqUByS73 cEBvKwZ81ZZ2ysBmPo/A8alv+dwl9+82AHa1yfZtyA== X-Google-Smtp-Source: AGRyM1v4cIDLFV47NrZB9iXVFbGEf3aeLxZU/leShv9g6OoM3E5E6lk0Y6aQuooL5k+W+rIKvIno1mH8opNY7YpLxCE= X-Received: by 2002:a17:907:160f:b0:726:9467:9be8 with SMTP id hb15-20020a170907160f00b0072694679be8mr12712385ejc.770.1657877073538; Fri, 15 Jul 2022 02:24:33 -0700 (PDT) MIME-Version: 1.0 References: <20220715052058.28405-1-samuel@sholland.org> <20220715052058.28405-4-samuel@sholland.org> In-Reply-To: <20220715052058.28405-4-samuel@sholland.org> From: Jagan Teki Date: Fri, 15 Jul 2022 14:54:21 +0530 Message-ID: Subject: Re: [PATCH 3/3] net: sun8i-emac: Use common syscon setup for R40 To: Samuel Holland Cc: u-boot@lists.denx.de, Andre Przywara , Joe Hershberger , Ramon Fried Content-Type: text/plain; charset="UTF-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Fri, Jul 15, 2022 at 10:51 AM Samuel Holland wrote: > > While R40 puts the EMAC syscon register at a different address from > other variants, the relevant portion of the register's layout is the > same. Factor out the register offset so the same code can be shared > by all variants. This matches what the Linux driver does. > > This change provides two benefits beyond the simplification: > - R40 boards now respect the RX delays from the devicetree > - This resolves a warning on architectures where readl/writel > expect the address to have a pointer type, not phys_addr_t. > > Signed-off-by: Samuel Holland > --- > > drivers/net/sun8i_emac.c | 29 ++++++++++++----------------- > 1 file changed, 12 insertions(+), 17 deletions(-) > > diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c > index 9cca8fa4e0a1..75ecb58e1e45 100644 > --- a/drivers/net/sun8i_emac.c > +++ b/drivers/net/sun8i_emac.c > @@ -162,7 +162,7 @@ struct emac_eth_dev { > > enum emac_variant variant; > void *mac_reg; > - phys_addr_t sysctl_reg; > + void *sysctl_reg; > struct phy_device *phydev; > struct mii_dev *bus; > struct clk tx_clk; > @@ -317,18 +317,7 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, > { > u32 reg; > > - if (priv->variant == R40_GMAC) { > - /* Select RGMII for R40 */ > - reg = readl(priv->sysctl_reg + 0x164); > - reg |= SC_ETCS_INT_GMII | > - SC_EPIT | > - (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET); > - > - writel(reg, priv->sysctl_reg + 0x164); > - return 0; > - } > - > - reg = readl(priv->sysctl_reg + 0x30); > + reg = readl(priv->sysctl_reg); > > reg = sun8i_emac_set_syscon_ephy(priv, reg); > > @@ -369,7 +358,7 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, > reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET) > & SC_ERXDC_MASK; > > - writel(reg, priv->sysctl_reg + 0x30); > + writel(reg, priv->sysctl_reg); > > return 0; > } > @@ -792,6 +781,7 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev) > struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev); > struct eth_pdata *pdata = &sun8i_pdata->eth_pdata; > struct emac_eth_dev *priv = dev_get_priv(dev); > + phys_addr_t syscon_base; > const fdt32_t *reg; > int node = dev_of_offset(dev); > int offset = 0; > @@ -837,13 +827,18 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev) > __func__); > return -EINVAL; > } > - priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob, > - offset, reg); > - if (priv->sysctl_reg == FDT_ADDR_T_NONE) { > + > + syscon_base = fdt_translate_address((void *)gd->fdt_blob, offset, reg); > + if (syscon_base == FDT_ADDR_T_NONE) { > debug("%s: Cannot find syscon base address\n", __func__); > return -EINVAL; > } > > + if (priv->variant == R40_GMAC) > + priv->sysctl_reg = (void *)syscon_base + 0x164; > + else > + priv->sysctl_reg = (void *)syscon_base + 0x30; > + Better to get syscon fields from driver data as this driver support DM. Jagan.