From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38B47C433F5 for ; Fri, 8 Oct 2021 13:22:51 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 19C3C60EE4 for ; Fri, 8 Oct 2021 13:22:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 19C3C60EE4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 276F683600; Fri, 8 Oct 2021 15:22:48 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="j3ZqtKn8"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id DA3DA83604; Fri, 8 Oct 2021 15:22:45 +0200 (CEST) Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4EF2A835A4 for ; Fri, 8 Oct 2021 15:22:42 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jagan@amarulasolutions.com Received: by mail-ed1-x531.google.com with SMTP id z20so36117437edc.13 for ; Fri, 08 Oct 2021 06:22:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Xq+w1rxelnzH3WajxmxJ4jT7i1xHigpjdBbsRXgtkyw=; b=j3ZqtKn80v3TA3lekbQvn1khroOWUyOiPmWUU15Q3or5UBo53SOJoUM3LMbpUvEMsb 1qwV8OVi64o4ItYGNLyZHOHjPO0k1syTYumOF9p2ZA0JK3+k4v6F/9JCI/yCTJ5HzZ0F Ddwn6Ba9ge4OREUefDrhPQwtf+X6yo/gxbqVg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Xq+w1rxelnzH3WajxmxJ4jT7i1xHigpjdBbsRXgtkyw=; b=6W0eocLR228P2RZpJBEHmy9MJCwo/hpl5xhocD4Hgjyl2570URCz4IUT8gY5TettWr +wFtN3r6bO/7JBxmKdqkktjuO4PUPzMK7tMjlc86Sm/Q6PKSzaGZmY4RxBWy77LGvQhN 5eFLdC7EK+++KpvWItMKp58sVJopKRFWDQo7S5HaK144SjPrRJSm8gH8JA40rnFKi1aA L3BBJ+oiUy0ifGzBuj/SHVB6aM4qfwG6mrz0VkhO6yFANkWCJOPUqKmxew+C6uXMTLfq 51UO1GbVsoYSJQMOXxpLN/dEF4Rx8A3NpDQoghd+GJ+avn2t/8/Y7YLFtutkoPsltiHS wNJg== X-Gm-Message-State: AOAM530S4Oa6XeYysmXHoeR1X8wDZc0LhY0/a/qoPPxTnNVEwh3ObeqZ hzLKcs/5pcW78yPx+Bcj0LkfdfcPmSUZ04AIkLK2k21pSiNPrw== X-Google-Smtp-Source: ABdhPJxzLXHKGKjA49Al9GY+0s0gHIDqOVMlyU6u/x/HQVISEY2sOPk/FTSwG/TASVH+ofRAgpGDaC82jBHFBjLxNtQ= X-Received: by 2002:a50:da8f:: with SMTP id q15mr15420547edj.139.1633699361890; Fri, 08 Oct 2021 06:22:41 -0700 (PDT) MIME-Version: 1.0 References: <20210930053228.10760-1-Takahiro.Kuwano@infineon.com> In-Reply-To: <20210930053228.10760-1-Takahiro.Kuwano@infineon.com> From: Jagan Teki Date: Fri, 8 Oct 2021 18:52:30 +0530 Message-ID: Subject: Re: [PATCH v2] mtd: spi-nor-core: Add fixups for s25fs512s To: Takahiro Kuwano Cc: U-Boot-Denx , Vignesh R , Pratyush Yadav , Bacem.Daassi@infineon.com, Takahiro Kuwano Content-Type: text/plain; charset="UTF-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On Thu, Sep 30, 2021 at 11:02 AM wrote: > > From: Takahiro Kuwano > > The current S25FS512S support has following issues that need to be fixed. > > - Non-uniform sectors by factory default. The setting needs to be > checked and assign erase hook as needed. > - Page size is wrongly advertised in SFDP. > - READ_1_1_2 (3Bh/3Ch), READ_1_1_4 (6Bh/6Ch), and PP_1_1_4 (32h/34h) > are not supported. > - Bank Address Register (BAR) is not supported. > > In addtion, volatile version of Quad Enable is used for safety. > > For future use, the fixups is assigned for S25FS-S family. > > The datasheet can be found in the following link. > https://www.cypress.com/file/216376/download > > Tested on Xilinx Zynq-7000 FPGA board. > > Signed-off-by: Takahiro Kuwano > --- > Changes in v2: > - Add #define S25FS_S_RDAR_DUMMY and remove hard-coding > - Remove #ifdef CONFIG_SPI_FLASH_BAR > > drivers/mtd/spi/spi-nor-core.c | 108 +++++++++++++++++++++++++++++++++ > 1 file changed, 108 insertions(+) > > diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c > index f1b4e5ea8e..349b2f3f23 100644 > --- a/drivers/mtd/spi/spi-nor-core.c > +++ b/drivers/mtd/spi/spi-nor-core.c > @@ -3099,6 +3099,109 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, > } > > #ifdef CONFIG_SPI_FLASH_SPANSION > + > +/* Number of dummy cycle for Read Any Register (RDAR) op. */ > +#define S25FS_S_RDAR_DUMMY 8 > + > +static int s25fs_s_quad_enable(struct spi_nor *nor) > +{ > + return spansion_quad_enable_volatile(nor, 0, S25FS_S_RDAR_DUMMY); > +} > + > +static int s25fs_s_erase_non_uniform(struct spi_nor *nor, loff_t addr) > +{ > + /* Support 8 x 4KB sectors at bottom */ > + return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0, > + SZ_32K); > +} > + > +static int s25fs_s_setup(struct spi_nor *nor, const struct flash_info *info, > + const struct spi_nor_flash_parameter *params) > +{ > + int ret; > + u8 cfr3v; > + > + /* Bank Address Register is not supported */ > + if (CONFIG_IS_ENABLED(SPI_FLASH_BAR)) > + return -ENOTSUPP; > + > + /* > + * Read CR3V to check if uniform sector is selected. If not, assign an > + * erase hook that supports non-uniform erase. > + */ > + ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V, > + S25FS_S_RDAR_DUMMY, &cfr3v); > + if (ret) > + return ret; > + if (!(cfr3v & CFR3V_UNHYSA)) > + nor->erase = s25fs_s_erase_non_uniform; > + > + return spi_nor_default_setup(nor, info, params); > +} > + > +static void s25fs_s_default_init(struct spi_nor *nor) > +{ > + nor->setup = s25fs_s_setup; > +} > + > +static int s25fs_s_post_bfpt_fixup(struct spi_nor *nor, > + const struct sfdp_parameter_header *header, > + const struct sfdp_bfpt *bfpt, > + struct spi_nor_flash_parameter *params) > +{ > + int ret; > + u8 cfr3v; > + > + /* The erase size is set to 4K from BFPT, but it's wrong. Fix it. */ > + nor->erase_opcode = SPINOR_OP_SE; > + nor->mtd.erasesize = nor->info->sector_size; > + > + if (params->size > SZ_16M) { > + ret = nor->write_reg(nor, SPINOR_OP_EN4B, NULL, 0); > + if (ret) > + return ret; > + nor->addr_width = 4; > + } else { > + nor->addr_width = 3; > + } > + > + /* > + * The page_size is set to 512B from BFPT, but it actually depends on > + * the configuration register. Look up the CFR3V and determine the > + * page_size. > + */ > + ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V, > + S25FS_S_RDAR_DUMMY, &cfr3v); > + if (ret) > + return ret; > + > + if (cfr3v & CFR3V_PGMBUF) > + params->page_size = 512; > + else > + params->page_size = 256; > + > + return 0; > +} > + > +static void s25fs_s_post_sfdp_fixup(struct spi_nor *nor, > + struct spi_nor_flash_parameter *params) > +{ > + /* READ_1_1_2 is not supported */ > + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2; > + /* READ_1_1_4 is not supported */ > + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4; > + /* PP_1_1_4 is not supported */ > + params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; > + /* Use volatile register to enable quad */ > + params->quad_enable = s25fs_s_quad_enable; > +} > + > +static struct spi_nor_fixups s25fs_s_fixups = { > + .default_init = s25fs_s_default_init, > + .post_bfpt = s25fs_s_post_bfpt_fixup, > + .post_sfdp = s25fs_s_post_sfdp_fixup, > +}; > + > static int s25hx_t_mdp_ready(struct spi_nor *nor) > { > u32 addr; > @@ -3646,6 +3749,11 @@ void spi_nor_set_fixups(struct spi_nor *nor) > break; > } > } > + > + /* For FS-S (family ID = 0x81) */ > + if (JEDEC_MFR(nor->info) == SNOR_MFR_SPANSION && > + nor->info->id[5] == 0x81) > + nor->fixups = &s25fs_s_fixups; Again, why cannot we add it in existing fixups? it that so different than from s25hx_t_fixups? Jagan.