From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05E3AC433EF for ; Mon, 25 Oct 2021 02:24:48 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4307560F11 for ; Mon, 25 Oct 2021 02:24:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 4307560F11 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2DE3182E7D; Mon, 25 Oct 2021 04:24:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="UHSCEbet"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4FBCB82EBB; Mon, 25 Oct 2021 04:24:43 +0200 (CEST) Received: from mail-il1-x12a.google.com (mail-il1-x12a.google.com [IPv6:2607:f8b0:4864:20::12a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 545D681F0B for ; Mon, 25 Oct 2021 04:24:39 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=rickchen36@gmail.com Received: by mail-il1-x12a.google.com with SMTP id h10so11241315ilq.3 for ; Sun, 24 Oct 2021 19:24:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=bKUcHf+dl06r2dFI5AZnI6ro9rv5j/KfaIZfrFErhK0=; b=UHSCEbet/6fsYkBRZhz8crufxKAhCnXoRyY4L1fMwvdCD+BneBR6MtXHbfSaxNulbZ qAP+JFiv13+Tvx+5no3gnMF4cf9fROtH/rYk4pYUWSp6AQIra0vN2YacqynrUqk0QpfV 7C7kZJZfHOI15DmvDotqhdGo89XN/O8IczkIoYShBSxq89vArPb1kY2tOJchW0hTC/44 OdkGfx5gIgbogKciOgdO3ivQ0nfNHCOMSJO4ltw/GAcrAnd45HDb29dOkiS8kATIfR+r GbKK9OEgclBzdHO/xjzUU1Ap6aOzT0K6J+uC3aluN0Q+DDCHOn1XVrDXjT0u+iuyAUVz RX9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=bKUcHf+dl06r2dFI5AZnI6ro9rv5j/KfaIZfrFErhK0=; b=2x8aZ0gIZJDUkPhJkM7eMhiAtB3rrpuX/iiiG2C9i9uWo7145r7lZvmZWeNC0og9yG NCDqtaV24CJNHDWZxTpjP9axJT7XlvoeLEK29W4v60DNEdRFYmQfJ51X//8uWuH+vUw0 nCBOkJM9dONd4V2QbGvJ78vnc1U0uXMl6JvfPARTlIBm8Swk30S+M2qoyLqBB6AqQ/99 hKuUpJciwlmuB5spXFGznQ2CSwwiDvOd/58eO+ww+QnT3uNoWhYsnEoKSECUrp6Q3UZV DPYBu3feODCQh8blBFvdvEWcbJKuogyIqPPVRSF5abd0rXhmDy7XOw26pX3LW9S1ha/T nNhA== X-Gm-Message-State: AOAM5327JeGoUiANf7/Iwv6zR931gNnsY+/0WzOcGgvTQvKqWpgOit2z tWTg+XSCXkhqkelVjcGYd0jyjE4bryZ4mzpWPro= X-Google-Smtp-Source: ABdhPJzsLOHohr/Lb8ZA9B72cZZr00Jt3MTYHjPC93evtxuV7yc+Riy0iGfPPbha9CoEN8RI0o22eTslch0Z7+WaX84= X-Received: by 2002:a92:a310:: with SMTP id a16mr8537210ili.273.1635128677949; Sun, 24 Oct 2021 19:24:37 -0700 (PDT) MIME-Version: 1.0 References: <20211001113745.52797-1-heinrich.schuchardt@canonical.com> In-Reply-To: From: Rick Chen Date: Mon, 25 Oct 2021 10:24:26 +0800 Message-ID: Subject: Re: [PATCH 1/1] board: sifive: unmatched: enlarge CONFIG_SYS_SPL_MALLOC_SIZE To: Bin Meng Cc: U-Boot Mailing List , Alexandre Ghiti , Tom Rini , Leo Liang , rick , Pragnesh Patel , Dimitri John Ledkov , Zong Li , Green Wan Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Hi, Bin > Hi Rick, > > On Mon, Oct 25, 2021 at 9:49 AM Rick Chen wrote: > > > > Hi Bin, > > > > > From: Bin Meng > > > Sent: Tuesday, October 19, 2021 4:55 PM > > > To: Alexandre Ghiti > > > Cc: Heinrich Schuchardt ; Tom Rini= ; Leo Yu-Chi Liang(=E6=A2=81=E8=82=B2=E9=BD=8A) ; Rick Jian-Zhi Chen(=E9=99=B3=E5=BB=BA=E5=BF=97) ; Pragnesh Patel ; Dimitri John Ledk= ov ; Zong Li ; Green Wan = ; U-Boot Mailing List > > > Subject: Re: [PATCH 1/1] board: sifive: unmatched: enlarge CONFIG_SYS= _SPL_MALLOC_SIZE > > > > > > On Tue, Oct 19, 2021 at 4:32 PM Alexandre Ghiti wrote: > > > > > > > > Hi, > > > > > > > > On Fri, Oct 1, 2021 at 5:35 PM Bin Meng wrote: > > > > > > > > > > Hi Heinrich, > > > > > > > > > > On Fri, Oct 1, 2021 at 7:37 PM Heinrich Schuchardt > > > > > wrote: > > > > > > > > > > > > Avoid an error like > > > > > > > > > > > > Could not get FIT buffer of 1725952 bytes > > > > > > check CONFIG_SYS_SPL_MALLOC_SIZE > > > > > > No device tree specified in SPL image > > > > > > ### ERROR ### Please RESET the board ### > > > > > > > > > > > > Signed-off-by: Heinrich Schuchardt > > > > > > > > > > > > --- > > > > > > include/configs/sifive-unmatched.h | 2 +- > > > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > > > > > diff --git a/include/configs/sifive-unmatched.h > > > > > > b/include/configs/sifive-unmatched.h > > > > > > index f8ad2cce1f..8d3deabdd3 100644 > > > > > > --- a/include/configs/sifive-unmatched.h > > > > > > +++ b/include/configs/sifive-unmatched.h > > > > > > @@ -18,7 +18,7 @@ > > > > > > #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 > > > > > > #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_A= DDR + \ > > > > > > CONFIG_SPL_BSS_MAX_SIZ= E) > > > > > > -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 > > > > > > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00200000 > > > > > > > > > > > > #define CONFIG_SPL_STACK (0x08000000 + 0x001D0000 - \ > > > > > > GENERATED_GBL_DATA_SIZE) > > > > > > > > > > What caused this? > > > > > > > > > > Last time this was seen on Ax25-AE350, CONFIG_SPL_SYS_MALLOC_F_LE= N > > > > > was increased, instead of CONFIG_SYS_SPL_MALLOC_SIZE which the er= ror > > > > > messages point to > > > > > > > > > > https://lists.denx.de/pipermail/u-boot/2021-May/449447.html > > > > > > > > > > > > > I fell into the same issue this morning and increasing > > > > CONFIG_SYS_SPL_MALLOC_SIZE fixed it, though I had to increase it ev= en > > > > more than Heinrich. > > > > > > Is this default build that caused Unmatched boot failure? > > > > > > @Rick Chen can you comment on why CONFIG_SPL_SYS_MALLOC_F_LEN was ne= eded on AE350? > > > > It is needed for limited memory cases on AE350 platforms. > > But the error message indicates that CONFIG_SYS_SPL_MALLOC_SIZE should > be increased, which is what this patch doing. > > Why is CONFIG_SYS_SPL_MALLOC_SIZE not working on AE350? I review why I increase SPL_SYS_MALLOC_F_LEN and recall that it will report memory size problem in spl_get_fit_load_buffer() of spl_fit.c. But Increase CONFIG_SYS_SPL_MALLOC_SIZE is helpful for boards with CONFIG_SYS_SPL_MALLOC_SIZE definition, On Ae350 it is not define SYS_SPL_MALLOC_SIZE, so I increase SPL_SYS_MALLOC_F_LEN instead. Thanks, Rick > > Regards, > Bin