From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E645EC54EE9 for ; Tue, 27 Sep 2022 11:36:15 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B740C84CFE; Tue, 27 Sep 2022 13:36:13 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="PZ62rnf3"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 6DC3384D68; Tue, 27 Sep 2022 13:36:12 +0200 (CEST) Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D2698836C5 for ; Tue, 27 Sep 2022 13:36:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=etienne.carriere@linaro.org Received: by mail-ed1-x52e.google.com with SMTP id z13so12719220edb.13 for ; Tue, 27 Sep 2022 04:36:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=YtVbpccoOrTRa8EvQUUtNnnmR7HcR2RCfJ4GFW8cY6k=; b=PZ62rnf3Unqu1C6y4xJbMqas5x1GcyFGTiH2k/5kXEp2YtoW8m3GOMa25HaueZyMUx t84YaIDDmAYbCsLv2fdxwU0eWaqNgiWY5JZouc9QLcsnZittsnzE3T1WbIy0Yu7RjRp8 9un6y/HroqwxFRTjAR+r7C8y9PO4yTGysHFMamRutZK/V7Xn0QqB7rbGY3wHPo/ZQaVV 2F5w4mF9Rc8jsD1v2PWz+VoDgKYd7yXNBf+VaEBBgw12pRO9mUsMgFdWIfr3CG9ONX9d FTjrBgBAeNsrAzULA56MlW9Ar6bSaUEay2KRSXyK/QhWCKDasyhtKtlHqbw7jk8N0sKW XXeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=YtVbpccoOrTRa8EvQUUtNnnmR7HcR2RCfJ4GFW8cY6k=; b=RpTTh8jf8kF+LIScWR+m3LjaQmQ+GyzeXtwltknohCWw9qZefe28jB2y52pPfHq1FD LkNk8FRwTo16SG0vUjyTott4rKGt8D9aorIsEmrGBIZr31fM/UoMPBFMMMWBZlRDEbfm C32c/7xG9oybJHdl6zgWPZCPbGtcZnesXeT3GfbpPYXB8ecUiezPNsiSsAM/bE3+8QAD BZ2li2edg6pS9XRWT++tWJzXicT8zhm4/jXHHIufEymZ7cpRrSZKj6DOOhthmcqCWhNR ezVTeiKn5qwqCkwfsyKsGTNDTFFtlMxUcoFhqDMGRqDg8jCy61+cn1GUzvMkitCfhHqw o6Mg== X-Gm-Message-State: ACrzQf0vm3KzsK/oQyeWN0LVsCtZ7IN+8UoXg0XKf4YAlVJzumkVtYZl gdDf+Mt5qWu/q3/NwC9pfAIUDQx1FjOoStrY9jE9Zg== X-Google-Smtp-Source: AMsMyM5ef7eJwiywpcrI8aWt3z7C/4ru5CSeXJr5TAUDCMpbQAAr5x89UsQM/yGe9OSjVO9SNwQuqAamdwZ3iZDCjW0= X-Received: by 2002:a05:6402:298:b0:457:9402:bb12 with SMTP id l24-20020a056402029800b004579402bb12mr2823453edv.379.1664278569339; Tue, 27 Sep 2022 04:36:09 -0700 (PDT) MIME-Version: 1.0 References: <20220915081451.633983-1-sughosh.ganu@linaro.org> <20220915081451.633983-8-sughosh.ganu@linaro.org> In-Reply-To: <20220915081451.633983-8-sughosh.ganu@linaro.org> From: Etienne Carriere Date: Tue, 27 Sep 2022 13:35:58 +0200 Message-ID: Subject: Re: [PATCH v10 07/15] FWU: STM32MP1: Add support to read boot index from backup register To: Sughosh Ganu Cc: u-boot@lists.denx.de, Heinrich Schuchardt , Ilias Apalodimas , Takahiro Akashi , Patrick Delaunay , Patrice Chotard , Simon Glass , Bin Meng , Tom Rini , Michal Simek , Jassi Brar Content-Type: text/plain; charset="UTF-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Thu, 15 Sept 2022 at 10:15, Sughosh Ganu wrote: > > The FWU Multi Bank Update feature allows the platform to boot the > firmware images from one of the partitions(banks). The first stage > bootloader(fsbl) passes the value of the boot index, i.e. the bank > from which the firmware images were booted from to U-Boot. On the > STM32MP157C-DK2 board, this value is passed through one of the SoC's > backup register. Add a function to read the boot index value from the > backup register. > > Signed-off-by: Sughosh Ganu > Reviewed-by: Patrick Delaunay > Acked-by: Ilias Apalodimas > --- > Changes since V9: > * Change the fwu_plat_get_bootidx() function to take an uint * as the > function parameter instead of the void * as suggested by Etienne. > > arch/arm/mach-stm32mp/include/mach/stm32.h | 5 +++++ > board/st/stm32mp1/stm32mp1.c | 23 ++++++++++++++++++++++ > include/fwu.h | 12 +++++++++++ > 3 files changed, 40 insertions(+) > > diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h > index c70375a723..c85ae6a34e 100644 > --- a/arch/arm/mach-stm32mp/include/mach/stm32.h > +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h > @@ -112,11 +112,16 @@ enum boot_device { > #ifdef CONFIG_STM32MP15x > #define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) > #define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) > +#define TAMP_FWU_BOOT_INFO_REG TAMP_BACKUP_REGISTER(10) > #define TAMP_COPRO_RSC_TBL_ADDRESS TAMP_BACKUP_REGISTER(17) > #define TAMP_COPRO_STATE TAMP_BACKUP_REGISTER(18) > #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20) > #define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(21) > > +#define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0) > + > +#define TAMP_FWU_BOOT_IDX_OFFSET 0 > + > #define TAMP_COPRO_STATE_OFF 0 > #define TAMP_COPRO_STATE_INIT 1 > #define TAMP_COPRO_STATE_CRUN 2 > diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c > index 6562bcf95b..54b9535405 100644 > --- a/board/st/stm32mp1/stm32mp1.c > +++ b/board/st/stm32mp1/stm32mp1.c > @@ -960,3 +960,26 @@ static void board_copro_image_process(ulong fw_image, size_t fw_size) > } > > U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process); > + > +#if defined(CONFIG_FWU_MULTI_BANK_UPDATE) > + > +#include > + > +/** > + * fwu_plat_get_bootidx() - Get the value of the boot index > + * @boot_idx: Boot index value > + * > + * Get the value of the bank(partition) from which the platform > + * has booted. This value is passed to U-Boot from the earlier > + * stage bootloader which loads and boots all the relevant > + * firmware images > + * > + */ > +void fwu_plat_get_bootidx(uint *boot_idx) > +{ > + u32 *bootidx = boot_idx; > + > + *bootidx = (readl(TAMP_FWU_BOOT_INFO_REG) >> > + TAMP_FWU_BOOT_IDX_OFFSET) & TAMP_FWU_BOOT_IDX_MASK; > +} I may be nitpicking but despite this is fine in this source file build only for 32bit, I think the cast is not that clean. Would prefer: void fwu_plat_get_bootidx(uint *boot_idx) { *boot_idx = (readl(TAMP_FWU_BOOT_INFO_REG) >> TAMP_FWU_BOOT_IDX_OFFSET) & TAMP_FWU_BOOT_IDX_MASK; } br, etienne > +#endif /* CONFIG_FWU_MULTI_BANK_UPDATE */ > diff --git a/include/fwu.h b/include/fwu.h > index 3ff37c628b..484289ed4f 100644 > --- a/include/fwu.h > +++ b/include/fwu.h > @@ -244,4 +244,16 @@ int fwu_plat_get_alt_num(struct udevice *dev, efi_guid_t *image_guid, > * > */ > int fwu_plat_get_update_index(uint *update_idx); > + > +/** > + * fwu_plat_get_bootidx() - Get the value of the boot index > + * @boot_idx: Boot index value > + * > + * Get the value of the bank(partition) from which the platform > + * has booted. This value is passed to U-Boot from the earlier > + * stage bootloader which loads and boots all the relevant > + * firmware images > + * > + */ > +void fwu_plat_get_bootidx(uint *boot_idx); > #endif /* _FWU_H_ */ > -- > 2.34.1 >