From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E7FBC43334 for ; Mon, 18 Jul 2022 17:26:47 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C0FB283E16; Mon, 18 Jul 2022 19:26:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="lHycPQpW"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 76A0883FEA; Mon, 18 Jul 2022 19:26:44 +0200 (CEST) Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 04B9083C10 for ; Mon, 18 Jul 2022 19:26:42 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=michael@amarulasolutions.com Received: by mail-wr1-x42d.google.com with SMTP id v16so18035941wrd.13 for ; Mon, 18 Jul 2022 10:26:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=stlbA3ES3sD90W+U7K66f++aXM8MXsQsxQ8V0AbbJzg=; b=lHycPQpWzmJ4vjA+tGQFJVs00LLSgZDkgU+KMTUowLaGw1wgpM79Hyxu2VZa2Ughr4 aXEO59uU45DJFb5JVJRAZem059fqWaa6oFizfBcDcsV3xmoM5JPife/4hHeUxKB0rQ0B eDXfZxk0NydxFeu3pXXcg3lmxHENOzzHUTZok= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=stlbA3ES3sD90W+U7K66f++aXM8MXsQsxQ8V0AbbJzg=; b=V+sOe8U5T1U8IxDkasH3eRp0ApBx4gSGPjYleZ1IQzfreh9gf/eKY8Z90SF4lRM+vr 0dDUQ3LXMwrBP7JWHn8i6N1Baf8JSLMGnd7Ssfd6ASxZnvJGplQ7DczbqXgbPc+edV6H JZ1rwyzuc7P1JKIgdXbbUr1jDhw0WXJlaf0nrO3L0uve35ynITuauD8Jl9aSOPsWXlnt kfRdiLB7mJgaLZAXzTq/itHPo7oTN23Ah5Cmrt5nwzcvlPybyE2rM+O7QfPtxYuPGUL/ mRADOACGnbuV+zMpoVYsUGk4vNjnyl4WY3M9IRhL0Tb3nslUmPJkblseNY8BkAvrseVk uedw== X-Gm-Message-State: AJIora9mbcQhnVCNN1cmfGCi3Jlqka/r5S0Hpfw7nw+8E0hj5sdiqKXh PUwKew3q6w3UA38R5x6vggREqphQQ+xhgwFh3f470g== X-Google-Smtp-Source: AGRyM1v5QFL/4uyjvp2h64ViAHNgiUGa4yfRjkjZE6AynZPVGE6A7L0PoM4EcglM/Mm2r12/nAynXvT9L+GWGlI69Oc= X-Received: by 2002:a5d:5586:0:b0:21e:294d:6003 with SMTP id i6-20020a5d5586000000b0021e294d6003mr1868060wrv.595.1658165201417; Mon, 18 Jul 2022 10:26:41 -0700 (PDT) MIME-Version: 1.0 References: <20220714031526.33697-1-samuel@sholland.org> <20220714031526.33697-3-samuel@sholland.org> <20220718172006.28729c32@donnerap.cambridge.arm.com> In-Reply-To: <20220718172006.28729c32@donnerap.cambridge.arm.com> From: Michael Nazzareno Trimarchi Date: Mon, 18 Jul 2022 19:26:29 +0200 Message-ID: Subject: Re: [PATCH 2/6] pinctrl: sunxi: Add NAND pinmuxes To: Andre Przywara Cc: Samuel Holland , u-boot@lists.denx.de, Jagan Teki , Dario Binacchi , Hans de Goede , Lukasz Majewski , Sean Anderson , Simon Glass Content-Type: text/plain; charset="UTF-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Hi Andre On Mon, Jul 18, 2022 at 6:20 PM Andre Przywara wrote: > > On Wed, 13 Jul 2022 22:15:22 -0500 > Samuel Holland wrote: > > Hi, > > > NAND is always at function 2 on port C. > > Indeed. > > > > > Pin lists and mux values were taken from the Linux drivers. > > Compared against the manuals. I didn't bother the check the pin ranges (I > think some additional CS pins were not covered by the comments), but that > shouldn't matter anyways. > > Reviewed-by: Andre Przywara > > > Signed-off-by: Samuel Holland > > Cheers, > Andre > > P.S.: I see that the A83T kernel pinctrl driver uses "nand" for *some* pins > instead of "nand0", not sure if that should to be fixed, or if it's too > late for that (not that NAND is mentioned at all in the A83T DT files ...) > Are you going to queue them all? Michael > > --- > > > > drivers/pinctrl/sunxi/pinctrl-sunxi.c | 13 +++++++++++++ > > 1 file changed, 13 insertions(+) > > > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c > > index 9ce2bc1b3afb..b10e3e7b0690 100644 > > --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c > > +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c > > @@ -268,6 +268,7 @@ static const struct sunxi_pinctrl_function sun4i_a10_pinctrl_functions[] = { > > #endif > > { "mmc2", 3 }, /* PC6-PC15 */ > > { "mmc3", 2 }, /* PI4-PI9 */ > > + { "nand0", 2 }, /* PC0-PC24 */ > > { "spi0", 3 }, /* PC0-PC2, PC23 */ > > #if IS_ENABLED(CONFIG_UART0_PORT_F) > > { "uart0", 4 }, /* PF2-PF4 */ > > @@ -292,6 +293,7 @@ static const struct sunxi_pinctrl_function sun5i_a13_pinctrl_functions[] = { > > { "mmc0", 2 }, /* PF0-PF5 */ > > { "mmc1", 2 }, /* PG3-PG8 */ > > { "mmc2", 3 }, /* PC6-PC15 */ > > + { "nand0", 2 }, /* PC0-PC19 */ > > { "spi0", 3 }, /* PC0-PC3 */ > > #if IS_ENABLED(CONFIG_UART0_PORT_F) > > { "uart0", 4 }, /* PF2-PF4 */ > > @@ -318,6 +320,7 @@ static const struct sunxi_pinctrl_function sun6i_a31_pinctrl_functions[] = { > > { "mmc1", 2 }, /* PG0-PG5 */ > > { "mmc2", 3 }, /* PC6-PC15, PC24 */ > > { "mmc3", 4 }, /* PC6-PC15, PC24 */ > > + { "nand0", 2 }, /* PC0-PC26 */ > > { "spi0", 3 }, /* PC0-PC2, PC27 */ > > #if IS_ENABLED(CONFIG_UART0_PORT_F) > > { "uart0", 3 }, /* PF2-PF4 */ > > @@ -361,6 +364,7 @@ static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = { > > { "mmc1", 4 }, /* PG0-PG5 */ > > #endif > > { "mmc2", 3 }, /* PC5-PC15, PC24 */ > > + { "nand0", 2 }, /* PC0-PC24 */ > > { "spi0", 3 }, /* PC0-PC2, PC23 */ > > #if IS_ENABLED(CONFIG_UART0_PORT_F) > > { "uart0", 4 }, /* PF2-PF4 */ > > @@ -384,6 +388,7 @@ static const struct sunxi_pinctrl_function sun8i_a23_pinctrl_functions[] = { > > { "mmc0", 2 }, /* PF0-PF5 */ > > { "mmc1", 2 }, /* PG0-PG5 */ > > { "mmc2", 3 }, /* PC5-PC16 */ > > + { "nand0", 2 }, /* PC0-PC16 */ > > { "spi0", 3 }, /* PC0-PC3 */ > > #if IS_ENABLED(CONFIG_UART0_PORT_F) > > { "uart0", 3 }, /* PF2-PF4 */ > > @@ -421,6 +426,7 @@ static const struct sunxi_pinctrl_function sun8i_a33_pinctrl_functions[] = { > > { "mmc0", 2 }, /* PF0-PF5 */ > > { "mmc1", 2 }, /* PG0-PG5 */ > > { "mmc2", 3 }, /* PC5-PC16 */ > > + { "nand0", 2 }, /* PC0-PC16 */ > > { "spi0", 3 }, /* PC0-PC3 */ > > #if IS_ENABLED(CONFIG_UART0_PORT_F) > > { "uart0", 3 }, /* PF2-PF4 */ > > @@ -447,6 +453,7 @@ static const struct sunxi_pinctrl_function sun8i_a83t_pinctrl_functions[] = { > > { "mmc0", 2 }, /* PF0-PF5 */ > > { "mmc1", 2 }, /* PG0-PG5 */ > > { "mmc2", 3 }, /* PC5-PC16 */ > > + { "nand0", 2 }, /* PC0-PC18 */ > > { "spi0", 3 }, /* PC0-PC3 */ > > #if IS_ENABLED(CONFIG_UART0_PORT_F) > > { "uart0", 3 }, /* PF2-PF4 */ > > @@ -487,6 +494,7 @@ static const struct sunxi_pinctrl_function sun8i_h3_pinctrl_functions[] = { > > { "mmc0", 2 }, /* PF0-PF5 */ > > { "mmc1", 2 }, /* PG0-PG5 */ > > { "mmc2", 3 }, /* PC5-PC16 */ > > + { "nand0", 2 }, /* PC0-PC16 */ > > { "spi0", 3 }, /* PC0-PC3 */ > > #if IS_ENABLED(CONFIG_UART0_PORT_F) > > { "uart0", 3 }, /* PF2-PF4 */ > > @@ -553,6 +561,7 @@ static const struct sunxi_pinctrl_function sun9i_a80_pinctrl_functions[] = { > > { "mmc0", 2 }, /* PF0-PF5 */ > > { "mmc1", 2 }, /* PG0-PG5 */ > > { "mmc2", 3 }, /* PC6-PC16 */ > > + { "nand0", 2 }, /* PC0-PC18 */ > > { "spi0", 3 }, /* PC0-PC2, PC19 */ > > #if IS_ENABLED(CONFIG_UART0_PORT_F) > > { "uart0", 4 }, /* PF2-PF4 */ > > @@ -592,6 +601,7 @@ static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = { > > { "mmc0", 2 }, /* PF0-PF5 */ > > { "mmc1", 2 }, /* PG0-PG5 */ > > { "mmc2", 3 }, /* PC1-PC16 */ > > + { "nand0", 2 }, /* PC0-PC16 */ > > { "pwm", 2 }, /* PD22 */ > > { "spi0", 4 }, /* PC0-PC3 */ > > #if IS_ENABLED(CONFIG_UART0_PORT_F) > > @@ -633,6 +643,7 @@ static const struct sunxi_pinctrl_function sun50i_h5_pinctrl_functions[] = { > > { "mmc0", 2 }, /* PF0-PF5 */ > > { "mmc1", 2 }, /* PG0-PG5 */ > > { "mmc2", 3 }, /* PC1-PC16 */ > > + { "nand0", 2 }, /* PC0-PC16 */ > > { "spi0", 3 }, /* PC0-PC3 */ > > #if IS_ENABLED(CONFIG_UART0_PORT_F) > > { "uart0", 3 }, /* PF2-PF4 */ > > @@ -659,6 +670,7 @@ static const struct sunxi_pinctrl_function sun50i_h6_pinctrl_functions[] = { > > { "mmc0", 2 }, /* PF0-PF5 */ > > { "mmc1", 2 }, /* PG0-PG5 */ > > { "mmc2", 3 }, /* PC1-PC14 */ > > + { "nand0", 2 }, /* PC0-PC16 */ > > { "spi0", 4 }, /* PC0-PC7 */ > > #if IS_ENABLED(CONFIG_UART0_PORT_F) > > { "uart0", 3 }, /* PF2-PF4 */ > > @@ -696,6 +708,7 @@ static const struct sunxi_pinctrl_function sun50i_h616_pinctrl_functions[] = { > > { "mmc0", 2 }, /* PF0-PF5 */ > > { "mmc1", 2 }, /* PG0-PG5 */ > > { "mmc2", 3 }, /* PC0-PC16 */ > > + { "nand0", 2 }, /* PC0-PC16 */ > > { "spi0", 4 }, /* PC0-PC7, PC15-PC16 */ > > #if IS_ENABLED(CONFIG_UART0_PORT_F) > > { "uart0", 3 }, /* PF2-PF4 */ > -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 michael@amarulasolutions.com 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