From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1C433ECAAD2 for ; Tue, 30 Aug 2022 02:31:07 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D1B8D84998; Tue, 30 Aug 2022 04:30:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="F9MY5fMH"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id B4A448497B; Tue, 30 Aug 2022 04:30:18 +0200 (CEST) Received: from mail-yw1-x112a.google.com (mail-yw1-x112a.google.com [IPv6:2607:f8b0:4864:20::112a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D978684986 for ; Tue, 30 Aug 2022 04:30:14 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@google.com Received: by mail-yw1-x112a.google.com with SMTP id 00721157ae682-340f82c77baso125281897b3.1 for ; Mon, 29 Aug 2022 19:30:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc; bh=FAbVJRw3kXE4E8bJkSf2rD5uKG33jv9G2OnXAxyvChE=; b=F9MY5fMH1k3QlxoGyTDgVE1GmTznKdX95UT9lk04kwu97OnDR3SEsYNjAXsYxVH2jZ SnYD4mRZFaEe6yN6aqU+g34e1vU3lO5QjlGWFRQ0PBy+71N3fFH9swH8FH26YRTDP1Hz o02mhOOXqUQxGHEgooA485DG3dOHnm8joQEJ0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc; bh=FAbVJRw3kXE4E8bJkSf2rD5uKG33jv9G2OnXAxyvChE=; b=zSuwo1AIfnwsLecsXZT/eeeXe9xb0UAlGLPRzCjjvbzAz0/5FZt2zmoqqf3QwMHafy p1/oCA/yI+qspJ0q0rnBJinDpU1imMg/LjrPVJPR0ro+6COdm05W6QaeCzvmJ6M0SsIu uSuXkaq8G6wiv3R28qszicbEFHLxK/KvAVKijkWBOlfYWKBFPtVqeleZ8NW+kVcd9tEC h2VF5X7EuX2X5dxlGnebCBh0yR6Rrlrh6jqrYrZmfaffxvRDmVGHkEdU8zpJc3FxmLiZ JN/ZqET9n6uOQvJ+1M+3Pc8NaS1lKuaF/itPOrGy3XGutk3b/ZUUj9Hb7G/CHcxQK0lx AejA== X-Gm-Message-State: ACgBeo3jzq7u/qcsg6a+x1gWjg2329jO/2n6R2MsOw44uozS+0X+TNAR jmHcU1IioRbhmIRLsoi2iNMam33tzYopYCoasnW+ZQ== X-Google-Smtp-Source: AA6agR7z122kH+BsI5Q3X2DkdZQ3VCq+khLqy1+ObgMT3MScD2NLMjj+RXcumjLnmR9yvF9R8gMQzgbTUp9QAdbe4Vg= X-Received: by 2002:a05:6902:18c:b0:695:9d04:c3e with SMTP id t12-20020a056902018c00b006959d040c3emr10248381ybh.58.1661826614258; Mon, 29 Aug 2022 19:30:14 -0700 (PDT) MIME-Version: 1.0 References: <20220406150911.23927-1-pali@kernel.org> <20220827123005.10239-1-pali@kernel.org> In-Reply-To: <20220827123005.10239-1-pali@kernel.org> From: Simon Glass Date: Mon, 29 Aug 2022 20:30:02 -0600 Message-ID: Subject: Re: [PATCH v2] pci: Do not enable PCIe GEN3 link retrain workaround by default To: =?UTF-8?Q?Pali_Roh=C3=A1r?= Cc: Stefan Roese , "Maciej W . Rozycki" , Bin Meng , U-Boot Mailing List Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Sat, 27 Aug 2022 at 06:30, Pali Roh=C3=A1r wrote: > > PCIe GEN3 link retrain workaround, specially designed for system with PCI= e > ASMedia ASM2824 Switch and other Endpoint devices, unconditionally increa= se > size of all SPL binaries with PCIe support, even those which do not requi= re it. > > Moreover this workaround is enabled for all existing hardware and also al= l > future PCIe hardware, which opens a hole that other PCIe vendors may > introduce same HW issue as on systems where this workaround is required a= nd > nobody would notice it because U-Boot automatically apply workaround for = it. > > So do not unconditionally enable this workaround on all hardware. Instead > introduce a new config option which is disabled by default. This decrease > SPL size and also ensure that workaround is not blindly or inexactly > enabled. > > To make workaround code local, move it into separate file, so pci_auto.c > contains only generic auto configuration code. > > Signed-off-by: Pali Roh=C3=A1r > --- > Changes in v2: > * Rename config option to CONFIG_PCIE_GEN3_RETRAIN_WORKAROUND as it is > generic workaround and does not have to be needed only for ASMedia swit= ch > (moreover it looks like issue is triggered by combination of ASMedia > switch with other endpoint PCIe device) > * Rephrase Kconfig help text as suggected by Stefan > --- > drivers/pci/Kconfig | 9 + > drivers/pci/Makefile | 1 + > drivers/pci/pci_auto.c | 171 +------------------ > drivers/pci/pcie_gen3_retrain_workaround.c | 183 +++++++++++++++++++++ > 4 files changed, 197 insertions(+), 167 deletions(-) > create mode 100644 drivers/pci/pcie_gen3_retrain_workaround.c Reviewed-by: Simon Glass