From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2DA0C54EE9 for ; Thu, 22 Sep 2022 03:33:19 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C4DF384CA9; Thu, 22 Sep 2022 05:33:17 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 1849E82FAB; Thu, 22 Sep 2022 05:33:16 +0200 (CEST) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8E83B82FAB for ; Thu, 22 Sep 2022 05:33:12 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 28M3WhHD070703; Thu, 22 Sep 2022 11:32:43 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from ubuntu01 (10.0.12.75) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 22 Sep 2022 11:32:42 +0800 Date: Thu, 22 Sep 2022 03:32:19 +0000 From: Leo Liang To: Andes CC: , , , , , , , , , Subject: Re: [PATCH 1/2] riscv: Introduce AVAILABLE_HARTS Message-ID: References: <20220921063455.7814-1-uboot@andestech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20220921063455.7814-1-uboot@andestech.com> User-Agent: Mutt/2.0.5 (2021-01-21) X-Originating-IP: [10.0.12.75] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 28M3WhHD070703 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Wed, Sep 21, 2022 at 02:34:54PM +0800, Andes wrote: > From: Rick Chen > > In SMP all harts will register themself in available_hart > during start up. Then main hart will send IPI to other harts > according to this variables. But this mechanism may not > guarantee that all other harts can jump to next stage. > > When main hart is sending IPI to other hart according to > available_harts, but other harts maybe still not finish the > registration. Then the SMP booting will miss some harts finally. > So let it become an option and it will be enabled by default. > > Please refer to the discussion: > https://www.mail-archive.com/u-boot@lists.denx.de/msg449997.html > > Signed-off-by: Rick Chen > --- > arch/riscv/Kconfig | 7 +++++++ > arch/riscv/cpu/cpu.c | 2 ++ > arch/riscv/cpu/start.S | 13 ++++++++----- > arch/riscv/include/asm/global_data.h | 2 ++ > arch/riscv/lib/asm-offsets.c | 2 ++ > arch/riscv/lib/smp.c | 2 ++ > 6 files changed, 23 insertions(+), 5 deletions(-) Reviewed-by: Leo Yu-Chi Liang