From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7DD9C433F5 for ; Thu, 7 Apr 2022 23:18:55 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id BB81883C0E; Fri, 8 Apr 2022 01:18:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=orcam.me.uk Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id A02F6811D8; Fri, 8 Apr 2022 01:18:52 +0200 (CEST) Received: from angie.orcam.me.uk (angie.orcam.me.uk [IPv6:2001:4190:8020::34]) by phobos.denx.de (Postfix) with ESMTP id 944F583C0E for ; Fri, 8 Apr 2022 01:18:49 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=orcam.me.uk Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=macro@orcam.me.uk Received: by angie.orcam.me.uk (Postfix, from userid 500) id 211D392009C; Fri, 8 Apr 2022 01:18:49 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by angie.orcam.me.uk (Postfix) with ESMTP id 142B292009B; Fri, 8 Apr 2022 00:18:49 +0100 (BST) Date: Fri, 8 Apr 2022 00:18:48 +0100 (BST) From: "Maciej W. Rozycki" To: Stefan Roese cc: =?UTF-8?Q?Pali_Roh=C3=A1r?= , Bin Meng , Simon Glass , u-boot@lists.denx.de Subject: Re: [PATCH] pci: Do not enable PCIe ASMedia ASM2824 workaround by default In-Reply-To: <0e7c3779-fb2e-4ef9-bcf0-08be2ce29bcb@denx.de> Message-ID: References: <20220406150911.23927-1-pali@kernel.org> <0e7c3779-fb2e-4ef9-bcf0-08be2ce29bcb@denx.de> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Thu, 7 Apr 2022, Stefan Roese wrote: > > Hello! What do you think about this change? I think it is good > > compromise between enable this workaround for all builds on all boards > > and enable it only based on device id. Or would it be better to restrict > > this workaround just for ASM2824 device like the last iteration of > > kernel patch? > > I'm not sure if we should name this "workaround" ASM2824, even though > it's currently (only) targeted exactly for this PCIe switch. It might > be helpful for other PCIe switches as well. So perhaps it's better to > give this function a more generic name instead? With this change, it > makes perhaps also sense to keep this function in pci_auto.c but also > rename the Kconfig option to some more generic version. By now I have become somewhat tired arguing and explaining matters over and over again as things have been moving as slow as molasses in this area, but one point I want to raise here is while it is indeed the ASM2824 device that seems problematic, it may actually be downstream, so you won't know it's there until you go through the workaround, as observed with the root port of the SiFive FU740-C000 SOC (which has a separate workaround in U-boot, clearly for the same issue; cf. `pcie_sifive_force_gen1'). So it looks like the erratum is going to show up with some device combinations in which the device enumerator may not have a way to know an ASM2824 is there until the workaround applied to an upstream device has let the link work. And as I previously already mentioned the Linux version of the workaround is only activated by the vendor:device ID because you cannot busy-loop polling on the Link Training bit in Linux (while you can do it in U-Boot, because U-Boot is not an OS). Arguably I could have broadened it to cover all Gen 3+ devices and poll on the Data Link Layer Link Active bit, which doesn't require busy-looping for meaningful results, but that would still leave Gen 2 devices out and chances are the system boots from U-Boot with the generic workaround applied and the link already negotiated at 2.5GT/s. NB the ASM2824 switch has been used with option cards as well, e.g. , so it can be there in any system that has a connector of any kind that lets one use PCIe option cards. FWIW, Maciej