From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D3F2C54EE9 for ; Sat, 17 Sep 2022 13:03:02 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4501D84BD4; Sat, 17 Sep 2022 15:02:55 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=orcam.me.uk Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id E6403849BC; Sat, 17 Sep 2022 15:02:53 +0200 (CEST) Received: from angie.orcam.me.uk (angie.orcam.me.uk [IPv6:2001:4190:8020::34]) by phobos.denx.de (Postfix) with ESMTP id C32D884A1A for ; Sat, 17 Sep 2022 15:02:51 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=orcam.me.uk Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=macro@orcam.me.uk Received: by angie.orcam.me.uk (Postfix, from userid 500) id A2BDD92009C; Sat, 17 Sep 2022 15:02:51 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by angie.orcam.me.uk (Postfix) with ESMTP id 9EC2192009B; Sat, 17 Sep 2022 14:02:51 +0100 (BST) Date: Sat, 17 Sep 2022 14:02:51 +0100 (BST) From: "Maciej W. Rozycki" To: Stefan Roese cc: =?UTF-8?Q?Pali_Roh=C3=A1r?= , Bin Meng , Simon Glass , u-boot@lists.denx.de Subject: Re: [PATCH v2] pci: Do not enable PCIe GEN3 link retrain workaround by default In-Reply-To: <7410275b-8057-e2ae-6b78-b867fcb9547d@denx.de> Message-ID: References: <20220406150911.23927-1-pali@kernel.org> <20220827123005.10239-1-pali@kernel.org> <20220830091900.7e4wyqonxonngo5d@pali> <7410275b-8057-e2ae-6b78-b867fcb9547d@denx.de> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Tue, 30 Aug 2022, Stefan Roese wrote: > > I think I wrote it. One issue is that it is increasing size of SPL image > > and we really should not include into SPL things which are not required > > for all target platforms. Lot of boards have size constrained memory > > requirements and unnecessary features should not be automatically > > enabled. > > I have to agree with Pali here. We need to be careful with size increase > in the SPL images, as some of the build targets are very limited here. > So making this workaround configurable is definitely a good idea. I object to having just a single workaround configurable as I expect it to be beyond the capability of people on average to get right. You simply start getting lost at one point, just as I am with all the random options the Linux kernel has nowadays. And the dozens added with every release. I agree on the SPL side and on a global option. I think it only makes sense to have individual workarounds selectable for onboard devices with hardware that has no external PCI/e connectivity. Those should not be exposed to the user and instead implicitly selected by the scriptery based on the base machine chosen. > The question remains, at least for me, if the Kconfig option should be > enable per default or not. For SPL my suggestions is to disable is per > default because of the size remarks above. For U-Boot proper I'm not so > sure. Please see below... FWIW Linux has a global PCI_QUIRKS option available in the expert mode only that lets one disable all workarounds: config PCI_QUIRKS default y bool "Enable PCI quirk workarounds" if EXPERT help This enables workarounds for various PCI chipset bugs/quirks. Disable this only if your target machine is unaffected by PCI quirks. for U-Boot I could envisage something like: config PCI_QUIRKS bool "Enable PCI quirk workarounds" if EXPERT default y if !SPL [...] Leaving just a single workaround out, especially for option card devices is asking for people getting it wrong. If there are individual workarounds required by hardware with no external PCI/e connectivity, then we could have say: config PCI_QUIRKS bool "Enable PCI quirk workarounds" if EXPERT default y if !SPL select SPECIFIC_QUIRK_FOR_BADLY_BROKEN_BOARD config BADLY_BROKEN_BOARD bool "Enable support for Badly Broken Board" select SPECIFIC_QUIRK_FOR_BADLY_BROKEN_BOARD config SPECIFIC_QUIRK_FOR_BADLY_BROKEN_BOARD bool and then wire the specific quirk to SPECIFIC_QUIRK_FOR_BADLY_BROKEN_BOARD rather than PCI_QUIRKS in the Makefile system. Thank you for your input. Maciej