From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34660C433EF for ; Fri, 12 Nov 2021 14:03:46 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8410760F55 for ; Fri, 12 Nov 2021 14:03:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 8410760F55 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B1B3782FC4; Fri, 12 Nov 2021 15:03:43 +0100 (CET) Authentication-Results: phobos.denx.de; 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Fri, 12 Nov 2021 15:03:28 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp102.mailbox.org (smtp102.mailbox.org [IPv6:2001:67c:2050:105:465:1:3:0]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-204.mailbox.org (Postfix) with ESMTPS id 4HrL0J1Dm0zQkDy; Fri, 12 Nov 2021 15:03:28 +0100 (CET) Message-ID: Date: Fri, 12 Nov 2021 15:03:24 +0100 MIME-Version: 1.0 Subject: Re: [PATCH u-boot-marvell 04/10] pci: pci_mvebu: Replace MBUS_PCI_*_SIZE by resource_size() Content-Language: en-US To: =?UTF-8?Q?Marek_Beh=c3=ban?= Cc: u-boot@lists.denx.de, =?UTF-8?Q?Pali_Roh=c3=a1r?= , =?UTF-8?Q?Marek_Beh=c3=ban?= References: <20211111153549.29111-1-kabel@kernel.org> <20211111153549.29111-5-kabel@kernel.org> From: Stefan Roese In-Reply-To: <20211111153549.29111-5-kabel@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.35 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On 11/11/21 16:35, Marek Behún wrote: > From: Pali Rohár > > Use more appropriate resource_size() function when working with data in > struct resource. > > Signed-off-by: Pali Rohár > Signed-off-by: Marek Behún Reviewed-by: Stefan Roese Thanks, Stefan > --- > drivers/pci/pci_mvebu.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c > index 97c7b5604f..fde52ec99d 100644 > --- a/drivers/pci/pci_mvebu.c > +++ b/drivers/pci/pci_mvebu.c > @@ -477,9 +477,9 @@ static int mvebu_pcie_probe(struct udevice *dev) > > if (mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr, > (phys_addr_t)pcie->mem.start, > - MBUS_PCI_MEM_SIZE)) { > + resource_size(&pcie->mem))) { > printf("PCIe unable to add mbus window for mem at %08x+%08x\n", > - (u32)pcie->mem.start, MBUS_PCI_MEM_SIZE); > + (u32)pcie->mem.start, (unsigned)resource_size(&pcie->mem)); > } > > pcie->io.start = (u32)mvebu_pcie_iobase; > @@ -488,9 +488,9 @@ static int mvebu_pcie_probe(struct udevice *dev) > > if (mvebu_mbus_add_window_by_id(pcie->io_target, pcie->io_attr, > (phys_addr_t)pcie->io.start, > - MBUS_PCI_IO_SIZE)) { > + resource_size(&pcie->io))) { > printf("PCIe unable to add mbus window for IO at %08x+%08x\n", > - (u32)pcie->io.start, MBUS_PCI_IO_SIZE); > + (u32)pcie->io.start, (unsigned)resource_size(&pcie->io)); > } > > /* Setup windows and configure host bridge */ > @@ -498,13 +498,13 @@ static int mvebu_pcie_probe(struct udevice *dev) > > /* PCI memory space */ > pci_set_region(hose->regions + 0, pcie->mem.start, > - pcie->mem.start, MBUS_PCI_MEM_SIZE, PCI_REGION_MEM); > + pcie->mem.start, resource_size(&pcie->mem), PCI_REGION_MEM); > pci_set_region(hose->regions + 1, > 0, 0, > gd->ram_size, > PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); > pci_set_region(hose->regions + 2, pcie->io.start, > - pcie->io.start, MBUS_PCI_IO_SIZE, PCI_REGION_IO); > + pcie->io.start, resource_size(&pcie->io), PCI_REGION_IO); > hose->region_count = 3; > > /* PCI Bridge support 32-bit I/O and 64-bit prefetch mem addressing */ > Viele Grüße, Stefan Roese -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de