From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 584B6C433EF for ; Wed, 15 Dec 2021 10:58:00 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 53F268309A; Wed, 15 Dec 2021 11:57:58 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1639565878; bh=dGuE84a9ss6WdJSeBXbZuteRwCdnvjgnjY93pf2RyR4=; h=Date:Subject:To:Cc:References:From:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=sWtOCiYoAWNsxwrGmpppUoLmhwsOz2yUkpDVvxVvhRf3Ns0nfrp+mw5nr28nLJ/0z PUU9v4FwqaPXSGiV+sik4c5eBnfXh9sXq2A4EgxbBEEfCKp8VfEdiNZaTYHZCa/ZF5 H8SQ48eYnMwGZ5lma0sXR/Uww8yNS5bFdMyYvB3UYHYRTEu25KvHRPIBjmvfsTHnr4 APvbp6qrMLV8elpj0O+Iz5LYsAgKAzUHxdVK4QDG+vCLVH3ULu4FObryR9i/hCXpnE 9iQ0cPVEn6Xvv6MIcesO8GHSqDD8dZTUhAz9oPzQ3W1g9DqnbTuzCT6liSXinRHGsB 6mePTvDwAESSg== Received: by phobos.denx.de (Postfix, from userid 109) id 208C68304C; Wed, 15 Dec 2021 11:57:56 +0100 (CET) Received: from mout-u-107.mailbox.org (mout-u-107.mailbox.org [91.198.250.252]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A63A5830C2 for ; Wed, 15 Dec 2021 11:57:49 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp1.mailbox.org (unknown [91.198.250.123]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-107.mailbox.org (Postfix) with ESMTPS id 4JDXJs2HsJzQlJ6; Wed, 15 Dec 2021 11:57:49 +0100 (CET) Message-ID: Date: Wed, 15 Dec 2021 11:57:45 +0100 MIME-Version: 1.0 Subject: Re: [PATCH u-boot-marvell 06/10] pci: pci_mvebu: Do not allow setting ROM BAR on PCI Bridge Content-Language: en-US To: =?UTF-8?Q?Marek_Beh=c3=ban?= Cc: u-boot@lists.denx.de, =?UTF-8?Q?Pali_Roh=c3=a1r?= , =?UTF-8?Q?Marek_Beh=c3=ban?= References: <20211111153549.29111-1-kabel@kernel.org> <20211111153549.29111-7-kabel@kernel.org> From: Stefan Roese In-Reply-To: <20211111153549.29111-7-kabel@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On 11/11/21 16:35, Marek Behún wrote: > From: Pali Rohár > > The PCI Bridge which represents mvebu PCIe Root Port has Expansion ROM > Base Address register at offset 0x30 but its meaning is different that > of PCI's Expansion ROM BAR register, although the address format of > the register is the same. > > In reality, this device does not have any configurable PCI BARs. So > ensure that write operation into BARs (including Expansion ROM BAR) is a > noop and registers always contain zero address which indicates that BARs > are unsupported. > > Fixes: a7b61ab58d5d ("pci: pci_mvebu: Properly configure and use PCI Bridge (PCIe Root Port)") > Signed-off-by: Pali Rohár > Signed-off-by: Marek Behún Applied to u-boot-marvell/master Thanks, Stefan > --- > drivers/pci/pci_mvebu.c | 55 +++++++++++++++++++++++------------------ > 1 file changed, 31 insertions(+), 24 deletions(-) > > diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c > index b545e62689..701a17dfb7 100644 > --- a/drivers/pci/pci_mvebu.c > +++ b/drivers/pci/pci_mvebu.c > @@ -93,7 +93,7 @@ struct mvebu_pcie { > unsigned int mem_attr; > unsigned int io_target; > unsigned int io_attr; > - u32 cfgcache[(0x34 - 0x10) / 4]; > + u32 cfgcache[(0x3c - 0x10) / 4]; > }; > > /* > @@ -189,20 +189,20 @@ static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, > } > > /* > - * mvebu has different internal registers mapped into PCI config space > - * in range 0x10-0x34 for PCI bridge, so do not access PCI config space > - * for this range and instead read content from driver virtual cfgcache > + * The configuration space of the PCI Bridge on primary (first) bus is > + * of Type 0 but the BAR registers (including ROM BAR) don't have the > + * same meaning as in the PCIe specification. Therefore do not access > + * BAR registers and non-common registers (those which have different > + * meaning for Type 0 and Type 1 config space) of the PCI Bridge and > + * instead read their content from driver virtual cfgcache[]. > */ > - if (busno == pcie->first_busno && offset >= 0x10 && offset < 0x34) { > + if (busno == pcie->first_busno && ((offset >= 0x10 && offset < 0x34) || > + (offset >= 0x38 && offset < 0x3c))) { > data = pcie->cfgcache[(offset - 0x10) / 4]; > debug("(addr,size,val)=(0x%04x, %d, 0x%08x) from cfgcache\n", > offset, size, data); > *valuep = pci_conv_32_to_size(data, offset, size); > return 0; > - } else if (busno == pcie->first_busno && > - (offset & ~3) == PCI_ROM_ADDRESS1) { > - /* mvebu has Expansion ROM Base Address (0x38) at offset 0x30 */ > - offset -= PCI_ROM_ADDRESS1 - PCIE_EXP_ROM_BAR_OFF; > } > > /* > @@ -269,17 +269,21 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf, > } > > /* > - * mvebu has different internal registers mapped into PCI config space > - * in range 0x10-0x34 for PCI bridge, so do not access PCI config space > - * for this range and instead write content to driver virtual cfgcache > + * As explained in mvebu_pcie_read_config(), PCI Bridge Type 1 specific > + * config registers are not available, so we write their content only > + * into driver virtual cfgcache[]. > + * And as explained in mvebu_pcie_probe(), mvebu has its own specific > + * way for configuring primary and secondary bus numbers. > */ > - if (busno == pcie->first_busno && offset >= 0x10 && offset < 0x34) { > + if (busno == pcie->first_busno && ((offset >= 0x10 && offset < 0x34) || > + (offset >= 0x38 && offset < 0x3c))) { > debug("Writing to cfgcache only\n"); > data = pcie->cfgcache[(offset - 0x10) / 4]; > data = pci_conv_size_to_32(data, value, offset, size); > /* mvebu PCI bridge does not have configurable bars */ > if ((offset & ~3) == PCI_BASE_ADDRESS_0 || > - (offset & ~3) == PCI_BASE_ADDRESS_1) > + (offset & ~3) == PCI_BASE_ADDRESS_1 || > + (offset & ~3) == PCI_ROM_ADDRESS1) > data = 0x0; > pcie->cfgcache[(offset - 0x10) / 4] = data; > /* mvebu has its own way how to set PCI primary bus number */ > @@ -297,10 +301,6 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf, > pcie->sec_busno); > } > return 0; > - } else if (busno == pcie->first_busno && > - (offset & ~3) == PCI_ROM_ADDRESS1) { > - /* mvebu has Expansion ROM Base Address (0x38) at offset 0x30 */ > - offset -= PCI_ROM_ADDRESS1 - PCIE_EXP_ROM_BAR_OFF; > } > > /* > @@ -424,13 +424,20 @@ static int mvebu_pcie_probe(struct udevice *dev) > * U-Boot cannot recognize as P2P Bridge. > * > * Note that this mvebu PCI Bridge does not have compliant Type 1 > - * Configuration Space. Header Type is reported as Type 0 and in > - * range 0x10-0x34 it has aliased internal mvebu registers 0x10-0x34 > - * (e.g. PCIE_BAR_LO_OFF) and register 0x38 is reserved. > + * Configuration Space. Header Type is reported as Type 0 and it > + * has format of Type 0 config space. > * > - * Driver for this range redirects access to virtual cfgcache[] buffer > - * which avoids changing internal mvebu registers. And changes Header > - * Type response value to Type 1. > + * Moreover Type 0 BAR registers (ranges 0x10 - 0x28 and 0x30 - 0x34) > + * have the same format in Marvell's specification as in PCIe > + * specification, but their meaning is totally different and they do > + * different things: they are aliased into internal mvebu registers > + * (e.g. PCIE_BAR_LO_OFF) and these should not be changed or > + * reconfigured by pci device drivers. > + * > + * So our driver converts Type 0 config space to Type 1 and reports > + * Header Type as Type 1. Access to BAR registers and to non-existent > + * Type 1 registers is redirected to the virtual cfgcache[] buffer, > + * which avoids changing unrelated registers. > */ > reg = readl(pcie->base + PCIE_DEV_REV_OFF); > reg &= ~0xffffff00; > Viele Grüße, Stefan Roese -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de