From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CE708C433EF for ; Thu, 12 May 2022 08:42:02 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9666083BC2; Thu, 12 May 2022 10:41:58 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=writeme.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; secure) header.d=mail.com header.i=@mail.com header.b="SxIUrMFy"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D97CD8438D; Thu, 12 May 2022 10:41:56 +0200 (CEST) Received: from mout.gmx.com (mout.gmx.com [74.208.4.200]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id DC449803EE for ; Thu, 12 May 2022 10:41:52 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=writeme.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sinan@writeme.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=mail.com; s=dbd5af2cbaf7; t=1652344908; bh=VNuWWD1iiSA6lHmMEhJ9nnfBchxmJHsiMWfm1xWeCXk=; h=X-UI-Sender-Class:Subject:To:References:From:Date:In-Reply-To; b=SxIUrMFy2rk4D/zm+g4Us7nW0GJcSaFLd3eQdBgdUJ0tR5bsq/Pv6p+SxkFJvwDm4 vBMswFnv+dH6RoMPpo3akFsKNoqGoJ5aKs6w0gmH6KzBG+rJpHwYsfuOvt3WSSa4Ap 9awWAFEp/in3x9vWMwNnUnqjWSavAJ5nNSOF0nHM= X-UI-Sender-Class: 214d933f-fd2f-45c7-a636-f5d79ae31a79 Received: from [192.168.1.26] ([176.42.27.81]) by smtp.mail.com (mrgmxus005 [74.208.5.15]) with ESMTPA (Nemesis) id 0MCsr7-1nh8JN1hxr-009dRN; Thu, 12 May 2022 10:41:48 +0200 Subject: Re: Bug in p1_p2_rdb_pc? Caching-inhibited bit for initial L2 SRAM entry in TLB To: =?UTF-8?Q?Pali_Roh=c3=a1r?= , Priyanka Jain , Wolfgang Denk , u-boot@lists.denx.de References: <20220405085737.s34rfws7rg2zhe2n@pali> <20220413092633.gmz4rqpiha4rwecb@pali> <20220414210539.4tggfctvfjjnewko@pali> <20220508150844.qqxg452rs4wtf5bs@pali> From: Sinan Akman Message-ID: Date: Thu, 12 May 2022 04:41:33 -0400 User-Agent: Mozilla/5.0 (X11; Linux i686; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20220508150844.qqxg452rs4wtf5bs@pali> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable Content-Language: en-US X-Provags-ID: V03:K1:lJDbTt7gZatlGEuNzJjJkg5rceekd6k4IujJouxb15l0ZyzG6iD N/Vn+KVOtDULcn3wJvXhyhwZFKKSF0zR4SgtSZj/u/wpKp6XccTonAuMPKFvttPoBxv9zBl FnWxo7tAaVpWI3oFlLUUQfxec/Yr4+HK4XWmb1KcK7wiN/oDqjGFcALXEIjYIKEzFXXeIgV /9zNT53vDSsNFeAA9KUAw== X-UI-Out-Filterresults: notjunk:1;V03:K0:T6er+WSO9Cw=:uVLpoyigwDua8dSgWQrrqz QmRREsMfo8IzAyAxiI3fOhMzzytUcmdRQ+XoBq7jWKLHFiHO3/IghvMpxleJlfU6G150tTI8U H03Enjvjx6LbSTH1+mXDIaUepwLy0CFhded3QjEek4U+oNEM/sVAzAmNInqq3OyQQm2pjGE5l Y6+srC0W67pEUQsn9X/Z1QtO9mL15CgJSKicL+b+gX0nvLXSvcVNnrcGY4VQMic7tBImT63z2 Ikxvc9IfsqUaQP5dDoFLfoTyvds0EJ5o25BgGtb0R8JPoiv60yhPOY/LWq3xvfNcMRkC8Zat7 o0dlCkFhRjgYXgxzlZsUJCiS/h4aAqK6tSE9/YqhIxuPi6o1oVBMgZYaWUEFNihTQBDpQPHSz LAtXfrfdDSXZRVNdwLzVnqsFqW7fFmU1DMgdRI1svsDtcdbTyBAYEUUmMJHsvg0gEyFFWRtY6 mkaOlMVwRNvNWPMYwqp7tLjY1IAVZJmgg+kyBJQcTp7rsqCdjcVDfXCfXyKby6NwNRmDDtSu7 X+ZlgGoXZkHIUlY49ORjfyKu0DbI3rWJzsajHTpw3N7wp8/KVAXvUhKEqUO7aujbjq2CJya/I QHS9MpLQAfGcdc5jUYnBJK88Yb3JgpEHsam/4N4ZL0D+SyyNefIctQazbg90uR0eQIHIt4/Ty C0ZYGHIu81g8yynVyJssXQOl4dgEJuEr26lDIFpOLynmvWXyQMwjbjt70llMj+ON/bRUkNWYK ySfTl3TpGbP1MthjfrDTdtaz5ct0wnJDdOJqGf5p0VRmQzU1gewxvVNrp7FVfSLWrbpvwpff+ 0sHXIHnBAIUu1A4UeLyEY4v5EQiGNV5rl5hJv37/0ZEF2q4bh9aOUUmggazbATyJIPRJrVbSl +JXHA4YYt/ukLGa4dr64y5CqfmSXDs5KjE8U9lR4Lp4L2GujSBGeWkXmlFbXZyufAxy9d+Q9x QYv4Zs4qgmdM8HqjtaYNusmd4BGCVtU/gSpId+HVvy8Kj6kmshLHFwa65J6x5/EWNnzNv+7yb EC2drCRLztNZRvwwweBqlr9/kEs/6HOxu5mkRswN9+OJ6FxeFZvtez0/wREzRKVWsN9Z+TZ0r RETc5sqQlDPzkg= X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean =C2=A0 Hi Pali On 2022-05-08 11:08 a.m., Pali Roh=C3=A1r wrote: > On Thursday 14 April 2022 23:05:39 Pali Roh=C3=A1r wrote: >> + Sinan >> >> On Wednesday 13 April 2022 11:26:33 Pali Roh=C3=A1r wrote: >>> On Tuesday 05 April 2022 10:57:37 Pali Roh=C3=A1r wrote: >>>> Hello! >>>> >>>> I suspect that there is a bug in board/freescale/p1_p2_rdb_pc/tlb.c c= ode >>>> which configures TLB entry for initial L2 SRAM. >>>> >>>> When L2 is 512 kB long (e.g. on P2020) then U-Boot *unsets* MAS2_I bi= t >>>> for first half of L2 and for second half of L2 U-Boot *sets* this bit= . >>>> >>>> See code: >>>> https://source.denx.de/u-boot/u-boot/-/blob/v2022.04/board/freescale/= p1_p2_rdb_pc/tlb.c#L99-104 >>>> >>>> I do not think that one part of L2 SRAM should be configured differen= tly >>>> as second part. Therefore I think that this is a bug in U-Boot code. >>>> >>>> Do you know is correct configuration of TLB entries for initial L2 SR= AM? >>>> >>>> MAS2_I is Caching-inhibited bit which is described as: >>>> >>>> Caching-inhibited: >>>> * 0 - Accesses to this page are considered cacheable. >>>> * 1 - The page is considered caching-inhibited. All loads and stores = to >>>> the page bypass the caches and are performed directly to main >>>> memory. A read or write to a caching-inhibited page affects on= ly >>>> the memory element specified by the operation. >>> Hello! I found EREF: A Programmer=E2=80=99s Reference Manual for Frees= cale Power >>> Architecture Processors Supports e500 core family (e500v1, e500v2, >>> e500mc, e5500, e6500) e200 core family document at NXP web: >>> >>> https://www.nxp.com/files-static/32bit/doc/ref_manual/EREF_RM.pdf >>> >>> And section "Cache and MMU Architecture" in part 7.3.1.2.2 Unable to >>> Lock Conditions (page 763) contains following information: >>> >>> If no exceptions occur and no overlocking condition exists, an attempt >>> to set a lock can fail if any of the following is true: >>> >>> =E2=80=A2 The target address is marked cache-inhibited, or the storage >>> attributes of the address uses a coherency protocol that does not >>> support locking >>> >>> So for me it looks like that L2 SRAM (which works at L2 with locked >>> cache lines) should not set MA2_I (cache-inhibited) bit. >>> >>> Any opinion? Or you do have some more information? > Hello! > > I looked at it again and it is more complicated as I initially thought. > > There are two options how L2 cache on P2020 may be used as SRAM. First > option is the classic way with locking lines, like it is done on other > architectures. Second option seems to be P1/P2 specific as it is *not* > documented in e500 core reference manual, but in P2020 SoC reference > manual, and this option changes L2 operation from Cache to Memory-Mapped > SRAM mode. > > Downloading P2020 reference manual (rev2) requires NXP account: > https://www.nxp.com/webapp/Download?colCode=3DP2020RM > > But some older version (rev0) can be found on internet, e.g.: > http://m4udit.dinauz.org/P2020RM_rev0.pdf > > I checked U-Boot code and it is for L2 SRAM configuration uses second > option, therefore not via L2 locked lines, but as L2 memory-mapping. > > P2020 reference manual in section "Memory-Mapped SRAM Coherency Rules" > contains: > > Accesses to memory-mapped SRAM are cacheable only in the correspondin= g > e500 L1 caches. External accesses must be marked cache-inhibited or b= e > performed with non-caching transactions. > > So based on the fact that L2 is in U-Boot in memory-mapped SRAM mode, > not in cache mode with locked lines and that P2020 RM explicitly says > that memory-mapped SRAM can be cacheable in L1, my understanding is that > TLB mapping for L2 SRAM should work with Caching-inhibited bit set and > also with unset (when unset then caching is disabled at L1 level). > > Is my deduction correct? > > Priyanka, Sinan, any idea? =C2=A0 I am still away from my boards but in few weeks I will take a deeper look at this. I need to run some test to see and understand how this is all implemented. =C2=A0 Thanks for all the work you do for P2020. =C2=A0 Regards =C2=A0 Sinan Akman