From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44854C433EF for ; Fri, 19 Nov 2021 01:36:46 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B612261AED for ; Fri, 19 Nov 2021 01:36:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org B612261AED Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1C0E282FD3; Fri, 19 Nov 2021 02:36:43 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 2C20682FCF; Fri, 19 Nov 2021 02:36:30 +0100 (CET) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 476C682A7A for ; Fri, 19 Nov 2021 02:36:17 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=weijie.gao@mediatek.com X-UUID: 9261e8ace72f44b282f611b2613c7c2a-20211119 X-UUID: 9261e8ace72f44b282f611b2613c7c2a-20211119 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 637107161; Fri, 19 Nov 2021 09:36:12 +0800 Received: from MTKMBS34N1.mediatek.inc (172.27.4.172) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 19 Nov 2021 09:36:11 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS34N1.mediatek.inc (172.27.4.172) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 19 Nov 2021 09:36:10 +0800 Received: from mcddlt001.gcn.mediatek.inc (10.19.240.15) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 19 Nov 2021 09:36:10 +0800 From: Weijie Gao To: CC: GSS_MTK_Uboot_upstream , Weijie Gao Subject: [PATCH v2 04/14] reset: mtmips: add reset controller support for MediaTek MT7621 SoC Date: Fri, 19 Nov 2021 09:36:07 +0800 Message-ID: X-Mailer: git-send-email 2.17.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-MTK: N X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.35 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This patch adds reset controller bits definition header file for MediaTek MT7621 SoC Signed-off-by: Weijie Gao --- v2 changes: none --- include/dt-bindings/reset/mt7621-reset.h | 38 ++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 include/dt-bindings/reset/mt7621-reset.h diff --git a/include/dt-bindings/reset/mt7621-reset.h b/include/dt-bindings/reset/mt7621-reset.h new file mode 100644 index 0000000000..e129c531fc --- /dev/null +++ b/include/dt-bindings/reset/mt7621-reset.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 MediaTek Inc. All rights reserved. + * + * Author: Weijie Gao + */ + +#ifndef _DT_BINDINGS_MT7621_RESET_H_ +#define _DT_BINDINGS_MT7621_RESET_H_ + +#define RST_PPE 31 +#define RST_SDXC 30 +#define RST_CRYPTO 29 +#define RST_AUX_STCK 28 +#define RST_PCIE2 26 +#define RST_PCIE1 25 +#define RST_PCIE0 24 +#define RST_GMAC 23 +#define RST_UART3 21 +#define RST_UART2 20 +#define RST_UART1 19 +#define RST_SPI 18 +#define RST_I2S 17 +#define RST_I2C 16 +#define RST_NFI 15 +#define RST_GDMA 14 +#define RST_PIO 13 +#define RST_PCM 11 +#define RST_MC 10 +#define RST_INTC 9 +#define RST_TIMER 8 +#define RST_SPDIFTX 7 +#define RST_FE 6 +#define RST_HSDMA 5 +#define RST_MCM 2 +#define RST_SYS 0 + +#endif /* _DT_BINDINGS_MT7621_RESET_H_ */ -- 2.17.1